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| this is information on a product in full production. september 2016 docid024738 rev 6 1/135 stm32f401xb stm32f401xc arm ? cortex ? -m4 32b mcu+fpu, 105 dmips, 256kb flash/64kb ram, 11 tims , 1 adc, 11 comm. interfaces datasheet - production data features ? dynamic efficiency line with bam (batch acquisition mode) ? 1.7 v to 3.6 v power supply ? -40 c to 85/105 c temperature range ? core: arm ? 32-bit cortex ? -m4 cpu with fpu, adaptive real-time accelerator (art accelerator?) allowing 0-wait state execution from flash memory, frequency up to 84 mhz, memory protection unit, 105 dmips/ 1.25 dmips/mhz (dhrystone 2.1), and dsp instructions ? memories ? up to 256 kbytes of flash memory ? 512 bytes of otp memory ? up to 64 kbytes of sram ? clock, reset and supply management ? 1.7 v to 3.6 v application supply and i/os ? por, pdr, pvd and bor ? 4-to-26 mhz crystal oscillator ? internal 16 mhz factory-trimmed rc ? 32 khz oscillator for rtc with calibration ? internal 32 khz rc with calibration ? power consumption ? run: 128 a/mhz (peripheral off) ? stop (flash in stop mode, fast wakeup time): 42 a typ @ 25 c; 65 a max @25 c ? stop (flash in deep power down mode, slow wakeup time): down to 10 a typ@ 25 c; 28 a max @25 c ? standby: 2.4 a @25 c / 1.7 v without rtc; 12 a @85 c @1.7 v ?v bat supply for rtc: 1 a @25 c ? 112-bit, 2.4 msps a/d co nverter: up to 16 channels ? general-purpose dma: 16-stream dma controllers with fifos and burst support ? up to 11 timers: up to six 16-bit, two 32-bit timers up to 84 mhz, each with up to 4 ic/oc/pwm or pulse counter and quadrature (incremental) encoder input, two watchdog timers (independent and window) and a systick timer ? debug mode ? serial wire debug (swd) & jtag interfaces ? cortex-m4 embedded trace macrocell? ? up to 81 i/o ports wit h interrupt capability ? all io ports 5 v tolerant ? up to 78 fast i/os up to 42 mhz ? up to 11 communica tion interfaces ? up to 3 i 2 c interfaces (1mbit/s, smbus/pmbus) ? up to 3 usarts (2 x 10.5 mbit/s, 1 x 5.25 mbit/s), iso 7816 interface, lin, irda, modem control) ? up to 4 spis (up to 42 mbits/s at f cpu = 84 mhz), spi2 and spi3 with muxed full- duplex i 2 s to achieve audio class accuracy via internal audio pll or external clock ? sdio interface ? advanced connectivity ? usb 2.0 full-speed device/host/otg controller with on-chip phy ? crc calculation unit ? 96-bit unique id ? rtc: subsecond accuracy, hardware calendar ? all packages are ecopack ? 2 table 1. device summary reference part number stm32f401xb stm32f401cb, stm32f401rb, STM32F401VB stm32f401xc stm32f401cc, stm32f401rc, stm32f401vc wlcsp49 lqfp10 0 (1414 mm) lqfp64 (1010 mm) ) % * $ ufqfpn48 (77 mm) ufbga100 (7x7 mm) (2.965x2.965 mm) www.st.com
docid024738 rev 6 2/135 stm32f401xb stm32f401xc contents 4 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 compatibility with stm32f4 series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 arm ? cortex ? -m4 with fpu core with embedded flash and sram . . . 15 3.2 adaptive real-time memory accelerator (art accelerator?) . . . . . . . . . 15 3.3 memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.4 embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.5 crc (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 16 3.6 embedded sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.7 multi-ahb bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.8 dma controller (dma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.9 nested vectored interrupt controller (nvic) . . . . . . . . . . . . . . . . . . . . . . . 17 3.10 external interrupt/event controller (exti) . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.11 clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.12 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.13 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.14 power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.14.1 internal reset on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.14.2 internal reset off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.15 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.15.1 regulator on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.15.2 regulator off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.15.3 regulator on/off and in ternal power supply super visor availability . . 24 3.16 real-time clock (rtc) and backup registers . . . . . . . . . . . . . . . . . . . . . . 24 3.17 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.18 v bat operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.19 timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.19.1 advanced-control timers (tim1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.19.2 general-purpose timers (timx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 contents stm32f401xb stm32f401xc 3/135 docid024738 rev 6 3.19.3 independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.19.4 window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.19.5 systick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.20 inter-integrated circuit interface (i2c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.21 universal synchronous/asynchronous re ceiver transmitters (usart) . . 28 3.22 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.23 inter-integrated sound (i 2 s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.24 audio pll (plli2s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.25 secure digital input/output interface (sdio) . . . . . . . . . . . . . . . . . . . . . . . 30 3.26 universal serial bus on-the-go full-speed (otg_fs) . . . . . . . . . . . . . . . . 30 3.27 general-purpose input/outputs (gpios) . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.28 analog-to-digital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.29 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.30 serial wire jtag debug port (swj-dp) . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.31 embedded trace macrocell? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4 pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.1.6 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.1.7 current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.3.2 vcap_1/vcap_2 external capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.3.3 operating conditions at power-up/power-down (regulator on) . . . . . . . 61 6.3.4 operating conditions at power-up / power-down (regulator off) . . . . . 62 6.3.5 embedded reset and power control bloc k characteristics . . . . . . . . . . . 62 docid024738 rev 6 4/135 stm32f401xb stm32f401xc contents 4 6.3.6 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.3.7 wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.3.8 external clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.3.9 internal clock source charac teristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.3.10 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.3.11 pll spread spectrum clock generatio n (sscg) characteristics . . . . . . 82 6.3.12 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.3.13 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.3.14 absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 87 6.3.15 i/o current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.3.16 i/o port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.3.17 nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 6.3.18 tim timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 6.3.19 communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 6.3.20 12-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 6.3.21 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 6.3.22 v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 6.3.23 embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 6.3.24 sd/sdio mmc card host interface (sdio) characteristics . . . . . . . . . 111 6.3.25 rtc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 7 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 7.1 wlcsp49 2.965x2.965 mm package information . . . . . . . . . . . . . . . . . . . . . .114 7.2 ufqfpn48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 7.3 lqfp64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 7.4 lqfp100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 7.5 ufbga100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 7.6 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 7.6.1 reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 8 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 list of tables stm32f401xb stm32f401xc 5/135 docid024738 rev 6 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. stm32f401xb/c features and peripheral counts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 3. regulator on/off and internal power supply superv isor availability. . . . . . . . . . . . . . . . . 24 table 4. timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 5. comparison of i2c analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 6. usart feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 7. legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 8. stm32f401xb/stm32f401xc pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 9. alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 10. stm32f401xb/stm32f401xc register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 11. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 12. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 13. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 14. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 15. features depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . . 60 table 16. vcap_1/vcap_2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 17. operating conditions at power-up / power-down (r egulator on) . . . . . . . . . . . . . . . . . . . . 61 table 18. operating conditions at power-up / power-down (r egulator off). . . . . . . . . . . . . . . . . . . . 62 table 19. embedded reset and power control block characterist ics. . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 20. typical and maximum current consumption, code with data processing (art accelerator disabled) running from sram - v dd =1.8v . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 21. typical and maximum current consumption, code with data processing (art accelerator disabled) running from sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 22. typical and maximum current consumption in run mode, code with data processing (art accelerator enabled except pr efetch) running from flash memory- v dd = 1.8 v . . . 65 table 23. typical and maximum current consumption in run mode, code with data processing (art accelerator enabled except pref etch) running from flash memory - v dd = 3.3 v . . 66 table 24. typical and maximum current consumption in run mode, code with data processing (art accelerator disabled) running from flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 25. typical and maximum current consumption in run mode, code with data processing (art accelerator enabled with prefetch) running fr om flash memory . . . . . . . . . . . . . . . . 67 table 26. typical and maximum current consumption in sleep mode . . . . . . . . . . . . . . . . . . . . . . . . 67 table 27. typical and maximum current consumptions in stop mode - v dd =1.8 v . . . . . . . . . . . . . . 68 table 28. typical and maximum current consumption in stop mode - v dd =3.3 v. . . . . . . . . . . . . . . 68 table 29. typical and maximum current consumption in standby mode - v dd =1.8 v . . . . . . . . . . . . 68 table 30. typical and maximum current consumption in standby mode - v dd =3.3 v . . . . . . . . . . . . 69 table 31. typical and maximum current consumptions in v bat mode. . . . . . . . . . . . . . . . . . . . . . . . 69 table 32. switching output i/o current cons umption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 33. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 34. low-power mode wakeup timings (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 35. high-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 36. low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 37. hse 4-26 mhz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 table 38. lse oscillator characteristics (f lse = 32.768 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 39. hsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 40. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 41. main pll characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 docid024738 rev 6 6/135 stm32f401xb stm32f401xc list of tables 6 table 42. plli2s (audio pll) characteristic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 43. sscg parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 44. flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 45. flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 46. flash memory programming with v pp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 47. flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 48. ems characteristics for lqfp100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 49. emi characteristics for wlcsp49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 50. emi characteristics for lqfp100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 51. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 52. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 53. i/o current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 54. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 55. output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 56. i/o ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 57. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 58. timx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 59. i 2 c characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 60. scl frequency (f pclk1 = 42 mhz, v dd = v dd_i2c = 3.3 v) . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 61. spi dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 62. i 2 s dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 63. usb otg fs startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 64. usb otg fs dc electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 65. usb otg fs electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 66. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 67. adc accuracy at f adc = 18 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 68. adc accuracy at f adc = 30 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 69. adc accuracy at f adc = 36 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 70. adc dynamic accuracy at f adc = 18 mhz - limited test conditions . . . . . . . . . . . . . . . . . 107 table 71. adc dynamic accuracy at f adc = 36 mhz - limited test conditions . . . . . . . . . . . . . . . . . 107 table 72. temperature sensor characteristic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 0 table 73. temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 table 74. v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 75. embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 76. internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 77. dynamic characteristics: sd / mmc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 78. rtc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 79. wlcsp49 - 49-ball, 2.965 x 2.965 mm, 0.4 mm pitch wafer level chip scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 80. wlcsp49 recommended pcb design rules (0.4 mm pi tch) . . . . . . . . . . . . . . . . . . . . . . 116 table 81. ufqfpn48 - 48-lead, 7 x 7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 82. lqfp64 - 64-pin, 10 x 10 mm, 64-pin low-profile quad flat package mechanical data. . . 121 table 83. lqpf100- 100-pin, 14 x 14 mm, 100-pin low-profile quad flat package mechanical data 124 table 84. ufbga100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table 85. ufbga100 recommended pcb design rules (0.5 mm pitch bga) . . . . . . . . . . . . . . . . . 127 table 86. package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 table 87. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 table 88. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 list of figures stm32f401xb stm32f401xc 7/135 docid024738 rev 6 list of figures figure 1. compatible board design for lqfp100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 2. compatible board design for lqfp64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 3. stm32f401xb/stm32f401xc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 4. multi-ahb matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 5. power supply supervisor interconnection with in ternal reset off . . . . . . . . . . . . . . . . . . . 19 figure 6. pdr_on control with internal re set off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 7. regulator off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 8. startup in regulator off: slow v dd slope - power-down reset risen after v cap_1 /v cap_2 stabilization. . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 9. startup in regulator off mode: fast v dd slope - power-down reset risen before v cap_1 /v cap_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . 23 figure 10. stm32f401xb/stm32f401xc wlcsp49 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 11. stm32f401xb/stm32f401xc ufqfpn48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 12. stm32f401xb/stm32f401xc lqfp64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 13. stm32f401xb/stm32f401xc lqfp100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 14. stm32f401xb/stm32f401xc ufbga100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 15. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 16. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 17. input voltage measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 18. power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 19. current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 20. external capacitor c ext . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 21. typical v bat current consumption (lse and rtc on) . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 22. high-speed external clock source ac timing diagra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 23. low-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 24. typical application with an 8 mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 25. typical application with a 32.768 khz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 26. acc hsi versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 27. acc lsi versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 28. pll output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 29. pll output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 30. ft i/o input ch aracteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 31. i/o ac characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 32. recommended nrst pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 33. i 2 c bus ac waveforms and measurement ci rcuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 34. spi timing diagram - slave mode and cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 35. spi timing diagram - slave mode and cpha = 1 (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 36. spi timing diagram - master mode (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 37. i 2 s slave timing diagram (philips protocol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 38. i 2 s master timing diag ram (philips protocol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 39. usb otg fs timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . 104 figure 40. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 41. typical connection diagram using the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 42. power supply and reference decoupling (v ref+ not connected to v dda ). . . . . . . . . . . . . 109 figure 43. power supply and reference decoupling (v ref+ connected to v dda ). . . . . . . . . . . . . . . . 110 figure 44. sdio high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 45. sd default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 46. wlcsp49 - 0.4 mm pitch wafer level chip scale package outline . . . . . . . . . . . . . . . . . . 114 docid024738 rev 6 8/135 stm32f401xb stm32f401xc list of figures 8 figure 47. wlcsp49 0.4 mm pitch wafer level chip scale recommended footprint . . . . . . . . . . . . . 115 figure 48. wlcsp49 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 figure 49. ufqfpn48 - 48-lead, 7 x 7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 figure 50. ufqfpn48 - 48-lead, 7 x 7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 figure 51. ufqfpn48 marking example (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 figure 52. lqfp64 - 64-pin, 10 x 10 mm, 64-pin low-profile quad flat package outline . . . . . . . . . . 120 figure 53. lqfp64 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1 figure 54. lqfp64 marking example (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 figure 55. lqfp100 - 100-pin, 14 x 14 mm, 100-pin low-profile quad flat package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 figure 56. lqfp100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 figure 57. lqpf100 marking example (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 figure 58. ufbga100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 figure 59. ufbga100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 figure 60. ufbga100 marking example (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 introduction stm32f401xb stm32f401xc 9/135 docid024738 rev 6 1 introduction this datasheet provides the description of the stm32f401xb/stm32f401xc line of microcontrollers. the stm32f401xb/stm32f401xc datasheet shou ld be read in conjunction with rm0368 reference manual which is available from the stmicroelectronics website www.st.com . it includes all information concerning flash memory programming. for information on the cortex ? -m4 core, please refer to the cortex ? -m4 programming manual (pm0214) available from www.st.com . docid024738 rev 6 10/135 stm32f401xb stm32f401xc description 53 2 description the stm32f401 x b/stm32f401 x c devices are based on the high-performance arm ? cortex ? -m4 32-bit risc core operating at a frequency of up to 84 mhz. the cortex ? -m4 core features a floating point unit (f pu) single precision which supports all arm single-precision data-processing instructions and data types. it al so implements a full set of dsp instructions and a memory protec tion unit (mpu) which enhances application security. the stm32f401xb/stm32f401xc incorporate high-speed embedded memories (up to 256 kbytes of flash memory, up to 64 kbytes of sram), and an extensive range of enhanced i/os and peripherals connected to two apb buses, two ahb buses and a 32-bit multi-ahb bus matrix. all devices offer one 12-bit adc, a low-pow er rtc, six general-purpose 16-bit timers including one pwm timer for motor control, tw o general-purpose 32-bit timers. they also feature standard and advanced communication interfaces. ? up to three i 2 cs ? up to four spis ? two full duplex i 2 ss. to achieve audio class accuracy, the i 2 s peripherals can be clocked via a dedicated internal audio pll or via an external clock to allow synchronization. ? three usarts ? sdio interface ? usb 2.0 otg full speed interface refer to table 2: stm32f401xb/c features and peripheral counts for the peripherals available for each part number. the stm32f401xb/stm32f401xc operate in the ?40 to +105 c temperature range from a 1.7 (pdr off) to 3.6 v power supply. a comprehensive set of power-saving mode allows the design of low-power applications. these features make the stm32f401xb/stm32 f401xc microcontrollers suitable for a wide range of applications: ? motor drive and application control ? medical equipment ? industrial applications: plc, inverters, circuit breakers ? printers, and scanners ? alarm systems, video intercom, and hvac ? home audio appliances ? mobile phone sensor hub figure 3 shows the general block diagram of the devices. description stm32f401xb stm32f401xc 11/135 docid024738 rev 6 table 2. stm32f401xb/c features and peripheral counts peripherals stm32f401xb stm32f401xc flash memory in kbytes 128 256 sram in kbytes system 64 timers general- purpose 7 advanced- control 1 communication interfaces spi/ i 2 s 3/2 (full duplex) 4/2 (full duplex) 3/2 (full duplex) 4/2 (full duplex) i 2 c3 usart 3 sdio - 1 - 1 usb otg fs 1 gpios 36 50 81365081 12-bit adc number of channels 1 10 16 10 16 maximum cpu frequency 84 mhz operating voltage 1.7 to 3.6 v operating temperatures ambient temperatures: ?40 to +85 c/?40 to +105 c junction temperature: ?40 to + 125 c package wlcsp49 ufqfpn48 lqfp64 ufbga100 lqfp100 wlcsp49 ufqfpn48 lqfp64 ufbga100 lqfp100 docid024738 rev 6 12/135 stm32f401xb stm32f401xc description 53 2.1 compatibility with stm32f4 series the stm32f401xb/stm32f401xc are fully software and feature compatible with the stm32f4 series (stm32f42x, stm32f43x, stm32f41x, stm32f405 and stm32f407) the stm32f401xb/stm32f401xc can be used as drop-in replacement of the other stm32f4 products but some slight changes have to be done on the pcb board. figure 1. compatible board design for lqfp100 package 0 6 9 3 ' 3 ' 3 ' 3 ' 3 % 3 % 3 % 3 % 3 ( 3 ( 3 ( 3 ( 3 ( 3 ( 3 % 9 & $ 3 9 6 6 9 ' ' 6 7 0 ) [ 3 % q r w d y d l o d e o h d q \ p r u h 5 h s o d f h g e \ 9 & $ 3 3 ' 3 ' 3 ' 3 ' 3 % 3 % 3 % 3 % 3 ( 3 ( 3 ( 3 ( 3 ( 3 ( 3 % 9 & $ 3 9 ' ' 6 7 0 ) 6 7 0 ) o l q h 6 7 0 ) 6 7 0 ) o l q h 6 7 0 ) 6 7 0 ) o l q h 6 7 0 ) 6 7 0 ) o l q h 9 ' ' 9 6 6 9 ' ' 9 6 6 3 % description stm32f401xb stm32f401xc 13/135 docid024738 rev 6 figure 2. compatible board design for lqfp64 package 9 l q f u h d v h g w r ? i ( 6 5 ? r u e h o r z & $ 3 0 6 9 9 6 6 9 6 6 6 7 0 ) [ 6 7 0 ) 6 7 0 ) o l q h 9 ' ' 9 ' ' 3 % q r w d y d l o d e o h d q \ p r u h 5 h s o d f h g e \ 9 & $ 3 3 & 3 & 3 & 3 $ 3 $ 9 ' ' 9 & $ 3 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 & 3 & 3 & 3 & 3 % 3 % 3 % 3 % 3 % 3 % 9 & $ 3 9 ' ' 3 & 3 & 3 & 3 $ 3 $ 9 ' ' 9 6 6 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 & 3 & 3 & 3 & 3 % 3 % 3 % 3 % 3 % 3 % 9 & $ 3 9 ' ' 9 6 6 3 % 9 ' ' 9 6 6 9 6 6 9 ' ' docid024738 rev 6 14/135 stm32f401xb stm32f401xc description 53 figure 3. stm32f401xb/stm 32f401xc block diagram 1. the timers connected to apb2 are clocked from timxclk up to 84 mhz, while the timers connected to apb1 are clocked from timxclk up to 42 mhz. * 3 , 2 3 2 5 7 $ $ + % $ 3 % ( ; 7 , 7 : . 8 3 x s w r $ ) 3 $ > @ 7 , 0 3 : 0 f r p s o f k d q q h o v 7 , 0 b & + > @ 1 f k d q q h o v 7 , 0 b & + > @ ( 7 5 % . , 1 d v $ ) 8 6 $ 5 7 5 ; 7 ; & . & 7 6 5 7 6 d v $ ) 6 3 , 0 2 6 , 0 , 6 2 6 & . 1 6 6 d v $ ) $ 3 % 0 + ] $ 3 % 0 + ] d q d o r j l q s x w v 9 ' ' 5 ( ) b $ ' & 0 2 6 , 6 ' 0 , 6 2 6 ' b h [ w 6 & . & . 1 6 6 : 6 0 & . d v $ ) 6 3 , 6 $ / $ 5 0 b 2 8 7 2 6 & b , 1 2 6 & b 2 8 7 9 ' ' $ 9 6 6 $ 1 5 6 7 v p f d u g l u ' $ e 9 % $ 7 w r 9 ' 0 $ 6 & / 6 ' $ 6 0 % $ d v $ ) , & 6 0 % 8 6 - 7 $ * 6 : $ 5 0 & r u w h [ 0 0 + ] 1 9 , & ( 7 0 0 3 8 7 5 $ & ( & / . 7 5 $ & ( ' > @ ' 0 $ 6 w u h d p v ) , ) 2 $ & & ( / & $ & + ( $ + % 0 + ] 8 6 $ 5 7 0 % s v 7 h p s h u d w x u h v h q v r u $ ' & , ) # 9 ' ' $ 3 2 5 3 ' 5 % 2 5 6 x s s o \ v x s h u y l v l r q # 9 ' ' $ 3 9 ' , q w 3 2 5 u h v h w ; 7 $ / n + ] 0 $ 1 $ * 7 5 7 & 5 & + 6 5 & / 6 3 : 5 l q w h u i d f h : ' * . # 9 % $ 7 # 9 ' ' $ # 9 ' ' $ : 8 5 h v h w f o r f n f r q w u r o 3 / / $ 3 % & / . 9 ' ' w r 9 9 6 6 9 & $ 3 9 r o w d j h u h j x o d w r u w r 9 9 ' ' 3 r z h u p d q d j p w # 9 ' ' 6 7 $ 0 3 % d f n x s u h j l v w h u $ + % e x v p d w u l [ 6 0 $ 3 % 0 + ] / 6 7 , 0 f k d q q h o v d v $ ) ) o d v k x s w r . % 7 , 0 7 , 0 7 , 0 7 , 0 ' % 8 6 0 6 9 ) 3 8 $ 3 % 0 + ] p d [ $ + % 0 + ] 1 - 7 5 6 7 - 7 ' , - 7 & . 6 : & / . - 7 ' 2 6 : ' - 7 ' 2 , % 8 6 6 % 8 6 ' 0 $ 6 w u h d p v ) , ) 2 3 % > @ 3 & > @ 3 + > @ * 3 , 2 3 2 5 7 % * 3 , 2 3 2 5 7 & * 3 , 2 3 2 5 7 + e 7 , 0 e 7 , 0 e v p f d u g l u ' $ 8 6 $ 5 7 f k d q q h o d v $ ) f k d q q h o d v $ ) 5 ; 7 ; & . d v $ ) , & 6 0 % 8 6 , & 6 0 % 8 6 6 & / 6 ' $ 6 0 % $ d v $ ) 6 & / 6 ' $ 6 0 % $ d v $ ) 6 3 , 6 0 2 6 , 6 ' 0 , 6 2 6 ' b h [ w 6 & . & . 1 6 6 : 6 0 & . d v $ ) 5 ; 7 ; d v $ ) & 7 6 5 7 6 d v $ ) 8 6 $ 5 7 v p f d u g l u ' $ e e e e f k d q q h o v f k d q q h o v ( 7 5 d v $ ) f k d q q h o v ( 7 5 d v $ ) f k d q q h o v ( 7 5 d v $ ) ' 0 $ $ + % $ 3 % / 6 2 6 & b , 1 2 6 & b 2 8 7 + & / . ; 7 $ / 2 6 & 0 + ] 6 5 $ 0 . % : : ' * $ 3 % & / . $ + % 3 & / . $ + % 3 & / . & 5 & 0 $ 2 / & & t o 6 0 $ 2 / . 3 $ ) / - - # & ) & / $ ; = # - $ # + a s ! & 5 3 " / 4 ' & 3 & ) & / 0 ( 9 $ 0 $ - ) $ 6 " 5 3 3 / & 6 3 , 0 2 6 , 0 , 6 2 6 & . 1 6 6 d v $ ) 3 ' > @ * 3 , 2 3 2 5 7 ' 3 ( > @ * 3 , 2 3 2 5 7 ( functional overview stm32f401xb stm32f401xc 15/135 docid024738 rev 6 3 functional overview 3.1 arm ? cortex ? -m4 with fpu core with embedded flash and sram the arm ? cortex ? -m4 with fpu processor is the latest generation of arm processors for embedded systems. it was developed to provide a low-cost platform that meets the needs of mcu implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. the arm ? cortex ? -m4 with fpu 32-bit risc proces sor features exceptional code- efficiency, delivering the high-performance expect ed from an arm core in the memory size usually associated with 8- and 16-bit devices. the processor supports a set of dsp instructions which allow efficient signal pr ocessing and complex algorithm execution. its single precision fpu (floating point unit) speeds up software development by using metalanguage development tools, while avoiding saturation. the stm32f401xb/stm32f401xc devices are compatible with all arm tools and software. figure 3 shows the general block diagram of the stm32f401xb/stm32f401xc. note: cortex ? -m4 with fpu is binary compatible with cortex ? -m3. 3.2 adaptive real-time memory accelerator (art accelerator?) the art accelerator? is a memory accelerator which is optimized for stm32 industry- standard arm ? cortex ? -m4 with fpu processors. it balances the inherent performance advantage of the arm ? cortex ? -m4 with fpu over flash memory technologies, which normally requires the processor to wait for the flash memory at higher frequencies. to release the processor full 105 dmips performance at this frequency, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 256-bit flash memory. based on coremark benchmark, the performance achieved thanks to the art accele rator is equivalent to 0 wait state program execution from flash memory at a cpu frequency up to 84 mhz. 3.3 memory protection unit the memory protection unit (mpu) is used to manage the cpu accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. this memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. the protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. the mpu is especially helpful for applications wh ere some critical or ce rtified code has to be protected against the misbehavior of other ta sks. it is usually managed by an rtos (real- time operating system). if a prog ram accesses a memory location that is prohibited by the mpu, the rtos can detect it and take action. in an rtos environment, the kernel can dynamically update the mpu area setting, based on the process to be executed. the mpu is optional and can be bypassed for applications that do not need it. docid024738 rev 6 16/135 stm32f401xb stm32f401xc functional overview 53 3.4 embedded flash memory the devices embed up to 256 kbytes of flas h memory available for storing programs and data. 3.5 crc (cyclic redundancy check) calculation unit the crc (cyclic redundancy check) calculation unit is used to get a crc code from a 32-bit data word and a fixed generator polynomial. among other applications, crc-based techniques are used to verify data transmission or storage integrity. in the scope of the en/iec 60335-1 standard, they offer a means of verifying the flash memory integrity. the c rc calculation unit help s compute a software signature during runtime, to be compared with a reference signature generated at link-time and stored at a given memory location. 3.6 embedded sram all devices embed: ? up to 64 kbytes of system sram which can be accessed (read/write) at cpu clock speed with 0 wait states 3.7 multi-ahb bus matrix the 32-bit multi-ahb bu s matrix interconnects all the masters (cpu, dmas) and the slaves (flash memory, ram, ahb and apb peripherals) and ensures a seamless and efficient operation even when several high-spe ed peripherals work simultaneously. figure 4. multi-ahb matrix $ 5 0 & r u w h [ 0 * 3 ' 0 $ * 3 ' 0 $ % x v p d w u l [ 6 6 6 6 6 6 6 , & 2 ' ( ' & 2 ' ( $ & & ( / ) o d v k 6 5 $ 0 $ + % s h u l s k 0 0 0 0 , e x v ' e x v 6 e x v ' 0 $ b 3 , ' 0 $ b 0 ( 0 ' 0 $ b 0 ( 0 ' 0 $ b 3 0 6 9 0 $ + % s h u l s k $ 3 % $ 3 % functional overview stm32f401xb stm32f401xc 17/135 docid024738 rev 6 3.8 dma controller (dma) the devices feature two general-purpose dual-port dmas (dma1 and dma2) with 8 streams each. they are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripher al transfers. they fe ature dedicated fifos for apb/ahb peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (ahb/apb). the two dma controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. the two dma controllers also have a double buffering feature, which autom ates the use and switching of two memory buffers without requiring any special code. each stream is connected to dedicated hardware dma requests, with support for software trigger on each stream. configuration is made by software and transfer sizes between source and destination are independent. the dma can be used with the main peripherals: ? spi and i 2 s ? i 2 c ? usart ? general-purpose, basic and advanced-control timers timx ? sd/sdio/mmc host interface ? adc 3.9 nested vectored inter rupt controller (nvic) the devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 62 maskable interrupt channels plus the 16 interrupt lines of the cortex ? - m4 with fpu. ? closely coupled nvic gives low-latency interrupt processing ? interrupt entry vector table address passed directly to the core ? allows early processing of interrupts ? processing of late arriving, higher-priority interrupts ? support tail chaining ? processor state automatically saved ? interrupt entry restored on interrupt exit with no instruction overhead this hardware block provides flexible interrupt management features with minimum interrupt latency. 3.10 external interrupt/ event controller (exti) the external interrupt/event controller consists of 21 edge-detector lines used to generate interrupt/event requests. each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. a pending register maintains the status of the interrupt requests. the exti can detect an external line with a pulse width shorter than the in ternal apb2 clock period. up to 81 gpios can be connected to the 16 external interrupt lines. docid024738 rev 6 18/135 stm32f401xb stm32f401xc functional overview 53 3.11 clocks and startup on reset the 16 mhz internal rc oscillator is selected as the default cpu clock. the 16 mhz internal rc oscillator is factory-tr immed to offer 1% accuracy at 25 c. the application can then select as system clock eit her the rc oscillator or an external 4-26 mhz clock source. this clock can be monitored for failure. if a failure is detected, the system automatically switches back to the internal rc oscillator and a so ftware interrupt is generated (if enabled). this clock source is input to a pll thus allowing to increase the frequency up to 84 mhz. similarly, full interrupt management of the pll clock entry is available when necessary (for example if an indirectly us ed external oscillator fails). several prescalers allow t he configuration of the two ahb buses, the high-speed apb (apb2) and the low-sp eed apb (apb1) domains. the maxi mum frequency of the two ahb buses is 84 mhz while the maximum frequency of the high-speed apb domains is 84 mhz. the maximum allowe d frequency of th e low-speed apb do main is 42 mhz. the devices embed a dedicated pll (plli2s ) which allows to achieve audio class performance. in this case, the i 2 s master clock can generate all standard sampling frequencies from 8 khz to 192 khz. 3.12 boot modes at startup, boot pins are used to select one out of three boot options: ? boot from user flash ? boot from system memory ? boot from embedded sram the bootloader is located in system memory. it is used to reprogram the flash memory by using either usart1(pa9/10), usart2(pd5/6), usb otg fs in device mode (pa11/12) through dfu (device firmware upgrade), i2 c1(pb6/7), i2c2(pb10/3), i2c3(pa8/pb4), spi1(pa4/5/6/7), spi2(pb12/13/14/ 15) or spi3(pa15, pc10/11/12). for more detailed information on the bootloader, refer to application note: an2606, stm32? microcontroller system memory boot mode . 3.13 power supply schemes ? v dd = 1.7 to 3.6 v: external power supply for i/os with the internal supervisor (por/pdr) disabled, provided externally through v dd pins. requires the use of an external power supply supervisor connected to the vdd and pdr_on pins. ? v dd = 1.8 to 3.6 v: external power supply for i/os and the internal regulator (when enabled), provided externally through v dd pins. ? v ssa , v dda = 1.7 to 3.6 v: external analog power supplies for adc, reset blocks, rcs and pll. v dda and v ssa must be connected to v dd and v ss , respectively, with decoupling technique. ? v bat = 1.65 to 3.6 v: power supply for rtc, external clock 32 khz oscillator and backup registers (through power switch) when v dd is not present. refer to figure 18: power supply scheme for more details. functional overview stm32f401xb stm32f401xc 19/135 docid024738 rev 6 3.14 power supply supervisor 3.14.1 internal reset on this feature is available for v dd operating voltage range 1.8 v to 3.6 v. the internal power supply supervisor is enabled by holding pdr_on high. the devices have an integrated power-on reset (por) / power-down reset (pdr) circuitry coupled with a brownout reset (bor) circuitry. at power-on, por is always active, and ensures proper operation starting from 1.8 v. after the 1.8 v por threshold level is reached, the option byte loading process st arts, either to confirm or modify default thresholds, or to disable bor permanently. three bor thresholds are available through option bytes. the devices remain in reset mode when v dd is below a specified threshold, v por/pdr or v bor , without the need for an external reset circuit. the devices also feature an embedded programma ble voltage detector (pvd) that monitors the v dd /v dda power supply and compares it to the v pvd threshold. an interrupt can be generated when v dd /v dda drops below the v pvd threshold and/or when v dd /v dda is higher than the v pvd threshold. the interrupt service routine can then generate a warning message and/or put the mcu into a safe state. the pvd is enabled by software. 3.14.2 internal reset off this feature is available only on packages featuring the pdr_on pin. the internal power-on reset (por) / power-down reset (pdr) circuitry is disabled by setting the pdr_on pin to low. an external power supply supervisor should monitor v dd and should maintain the device in reset mode as long as v dd is below a specified threshold. pdr_on should be connected to this external power supply supervisor. refer to figure 5: power supply supervisor interconnection with internal reset off . figure 5. power supply supervisor inte rconnection with internal reset off (1) 1. the prd_on pin is only available on the wlcsp49 and ufbga100 packages. 0 6 9 1 5 6 7 3 ' 5 b 2 1 ( [ w h u q d o 9 ' ' s r z h u v x s s o \ v x s h u y l v r u ( [ w u h v h w f r q w u r o o h u d f w l y h z k h q 9 ' ' 9 9 ' ' $ s s o l f d w l r q u h v h w v l j q d o r s w l r q d o docid024738 rev 6 20/135 stm32f401xb stm32f401xc functional overview 53 the v dd specified threshold, below which the device must be maintained under reset, is 1.7 v (see figure 6 ). a comprehensive set of power-saving mode allows to design low-power applications. when the internal reset is off, the following integrated features are no longer supported: ? the integrated power-on reset (por) / power-down reset (pdr) circuitry is disabled. ? the brownout reset (bor) circuitry must be disabled. ? the embedded programmable voltage detector (pvd) is disabled. ? v bat functionality is no more available and vbat pin should be connected to v dd . 3.15 voltage regulator the regulator has four operating modes: ? regulator on ? main regulator mode (mr) ? low power regulator (lpr) ? power-down ? regulator off figure 6. pdr_on control with internal reset off 0 6 9 9 ' ' w l p h 3 ' 5 9 w l p h 1 5 6 7 3 ' 5 b 2 1 3 ' 5 b 2 1 5 h v h w e \ r w k h u v r x u f h w k d q s r z h u v x s s o \ v x s h u y l v r u functional overview stm32f401xb stm32f401xc 21/135 docid024738 rev 6 3.15.1 regulator on on packages embedding the bypass_reg pin, the regulator is enabled by holding bypass_reg low. on all ot her packages, the regula tor is always enabled. there are three power modes configured by software when the regulator is on: ? mr is used in the nominal regulation mode (with different voltage scaling in run) in main regulator mode (mr mode), different voltage scaling are provided to reach the best compromise between maximum fr equency and dynamic power consumption. ? lpr is used in the stop modes the lp regulator mode is configured by software when entering stop mode. ? power-down is used in standby mode. the power-down mode is activated only when entering in standby mode. the regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption. the contents of th e registers and sram are lost. depending on the package, one or two external ceramic capacitors should be connected on the v cap_1 and v cap_2 pins. the v cap_2 pin is only available for the lqfp100 and ufbga100 packages. all packages have the regulator on feature. 3.15.2 regulator off the regulator off is availa ble only on the ufbga100, which features the bypass_reg pin. the regulator is disabled by holding bypass_reg high. the regulator off mode allows to supply externally a v12 voltage source through v cap_1 and v cap_2 pins. since the internal voltage scaling is not managed internally, the external voltage value must be aligned with the targeted maximum frequency. refer to table 14: general operating conditions . the two 2.2 f v cap ceramic capacitors should be replaced by two 100 nf decoupling capacitors. refer to figure 18: power supply scheme . when the regulator is off, there is no more internal monitoring on v12. an external power supply supervisor should be used to monito r the v12 of the logic power domain. pa0 pin should be used for this purpose, and act as power-on reset on v12 power domain. in regulator off mode, the following features are no more supported: ? pa0 cannot be used as a gpio pin since it allows to reset a part of the v12 logic power domain which is not reset by the nrst pin. ? as long as pa0 is kept low, the debug mode cannot be used under power-on reset. as a consequence, pa0 and nrst pins must be managed separately if the debug connection under reset or pre-reset is required. docid024738 rev 6 22/135 stm32f401xb stm32f401xc functional overview 53 figure 7. regulator off the following conditions must be respected: ? v dd should always be higher than v cap_1 and v cap_2 to avoid current injection between power domains. ? if the time for v cap_1 and v cap_2 to reach v 12 minimum value is faster than the time for v dd to reach 1.7 v, then pa0 should be kept low to cover both conditions: until v cap_1 and v cap_2 reach v 12 minimum value and until v dd reaches 1.7 v (see figure 8 ). ? otherwise, if the time for v cap_1 and v cap_2 to reach v 12 minimum value is slower than the time for v dd to reach 1.7 v, then pa0 could be asserted low externally (see figure 9 ). ? if v cap_1 and v cap_2 go below v 12 minimum value and v dd is higher than 1.7 v, then a reset must be asserted on pa0 pin. note: the minimum value of v 12 depends on the maximum frequency targeted in the application d l 9 % < 3 $ 6 6 b 5 ( * 9 & $ 3 b 9 & $ 3 b 3 $ 9 9 ' ' 1 5 6 7 9 ' ' $ s s o l f d w l r q u h v h w v l j q d o r s w l r q d o ( [ w h u q d o 9 & $ 3 b s r z h u v x s s o \ v x s h u y l v r u ( [ w u h v h w f r q w u r o o h u d f w l y h z k h q 9 & $ 3 b 0 l q 9 9 functional overview stm32f401xb stm32f401xc 23/135 docid024738 rev 6 figure 8. startup in regulator off: slow v dd slope - power-down reset risen after v cap_1 /v cap_2 stabilization 1. this figure is valid whatever the internal reset mode (on or off). figure 9. startup in regulator off mode: fast v dd slope - power-down reset risen before v cap_1 /v cap_2 stabilization 1. this figure is valid whatever the internal reset mode (on or off). 0 6 y 9 9 ' ' w l p h 0 l q 9 3 ' 5 9 9 & $ 3 b 9 & $ 3 b 9 1 5 6 7 w l p h 9 ' ' w l p h 0 l q 9 9 & $ 3 b 9 & $ 3 b 9 3 $ d v v h u w h g h [ w h u q d o o \ 1 5 6 7 w l p h 0 6 y 9 3 ' 5 9 docid024738 rev 6 24/135 stm32f401xb stm32f401xc functional overview 53 3.15.3 regulator on/off and internal power supply supervisor availability 3.16 real-time clock (rtc ) and backup registers the backup domain includes: ? the real-time clock (rtc) ? 20 backup registers the real-time clock (rtc) is an independent bc d timer/counter. dedica ted registers contain the second, minute, hour (in 12/24 hour), we ek day, date, month, year, in bcd (binary- coded decimal) format. correction for 28, 29 (leap year), 30, and 31 day of the month are performed automatically. the rtc features a reference clock detection, a more precise second source clock (50 or 60 hz) can be us ed to enhance the calendar precision. the rtc provides a programmable alarm and programmable periodic interrupts with wakeup from stop and standby modes. the sub-seconds value is also available in binary format. it is clocked by a 32.768 khz external crystal, resonator or oscillator, the internal low-power rc oscillator or the high -speed external clock divided by 128. the internal low-speed rc has a typical frequency of 32 khz. the rtc can be calibrated using an external 512 hz output to compensa te for any natural quartz deviation. two alarm registers are used to generate an alar m at a specific time and calendar fields can be independently masked for alarm comparison. to generate a periodic interrupt, a 16-bit programmable binary auto-reload downcounter with programmable resolution is available and allows automatic wakeup and periodic alarms from every 120 s to every 36 hours. a 20-bit prescaler is used for the time base cl ock. it is by default configured to generate a time base of 1 second from a clock at 32.768 khz. the backup registers are 32-bit registers used to store 80 bytes of user application data when v dd power is not present. backup registers are not reset by a system, a power reset, or when the device wakes up from the standby mode (see section 3.17: low-power modes ). additional 32-bit registers contain the prog rammable alarm subseconds, seconds, minutes, hours, day, and date. table 3. regulator on/off and internal power supply supervisor availability package regulator on regulator off power supply supervisor on power supply supervisor off ufqfpn48 yes no yes no wlcsp49 yes no yes pdr_on set to vdd yes pdr_on external control (1) lqfp64 yes no yes no lqfp100 yes no yes no ufbga100 yes bypass_reg set to vss yes bypass_reg set to vdd yes pdr_on set to vdd yes pdr_on external control (1) 1. refer to section 3.14: power supply supervisor functional overview stm32f401xb stm32f401xc 25/135 docid024738 rev 6 the rtc and backup registers are supplied through a switch that is powered either from the v dd supply when present or from the v bat pin. 3.17 low-power modes the devices support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: ? sleep mode in sleep mode, only the cpu is stopped. all peripherals continue to operate and can wake up the cpu when an interrupt/event occurs. ? stop mode the stop mode achieves the lowest power consumption while retaining the contents of sram and registers. all clocks in the 1.2 v domain are stopped, the pll, the hsi rc and the hse crystal oscillators are disabled . the voltage regulator can also be put either in normal or in low-power mode. the devices can be woken up from the stop mode by any of the exti line (the exti line source can be one of the 16 external lines, the pvd output, the rtc alarm/ wakeup/ tamper/ time stamp events). ? standby mode the standby mode is used to achieve the lowest power consumption. the internal voltage regulator is switched off so that the entire 1.2 v domain is powered off. the pll, the hsi rc and the hse crystal oscillato rs are also switched off. after entering standby mode, the sram and register conten ts are lost except for registers in the backup domain when selected. the devices exit the standby mode when an external reset (nrst pin), an iwdg reset, a rising edge on the wkup pin, or an rtc alarm/ wakeup/ tamper/time stamp event occurs. standby mode is not supported when the embedded voltage regulator is bypassed and the 1.2 v domain is controlled by an external power. 3.18 v bat operation the vbat pin allows to power the device v bat domain from an external battery, an external super-capacitor, or from v dd when no external battery and an external super-capacitor are present. v bat operation is activated when v dd is not present. the vbat pin supplies the rtc and the backup registers. note: when the microcontroller is supplied from vba t, external interrupts and rtc alarm/events do not exit it from v bat operation. when pdr_on pin is not connected to v dd (internal reset off), the v bat functionality is no more available and vbat pin should be connected to v dd . docid024738 rev 6 26/135 stm32f401xb stm32f401xc functional overview 53 3.19 timers and watchdogs the devices embed one advanced-control time r, seven general-purpose timers and two watchdog timers. all timer counters can be frozen in debug mode. table 4 compares the features of the advanced-control and general-purpose timers. 3.19.1 advanced-control timers (tim1) the advanced-control timer (tim1) can be seen as three-phase pwm generators multiplexed on 4 independent channels. it has complementary pwm outputs with programmable inserted dead times. it can also be considered as a complete general- purpose timer. its 4 independent channels can be used for: ? input capture ? output compare ? pwm generation (edge- or center-aligned modes) ? one-pulse mode output table 4. timer feature comparison timer type timer counter resolution counter type prescaler factor dma request generation capture/ compare channels complemen- tary output max. interface clock (mhz) max. timer clock (mhz) advanced -control tim1 16-bit up, down, up/down any integer between 1 and 65536 yes 4 yes 84 84 general purpose tim2, tim5 32-bit up, down, up/down any integer between 1 and 65536 yes 4 no 42 84 tim3, tim4 16-bit up, down, up/down any integer between 1 and 65536 yes 4 no 42 84 tim9 16-bit up any integer between 1 and 65536 no 2 no 84 84 tim10, tim11 16-bit up any integer between 1 and 65536 no 1 no 84 84 functional overview stm32f401xb stm32f401xc 27/135 docid024738 rev 6 if configured as standard 16-bit timers, it has the same features as the general-purpose timx timers. if configured as a 16-bit pwm g enerator, it has full mo dulation capability (0- 100%). the advanced-control timer can work togethe r with the timx timers via the timer link feature for synchronizat ion or event chaining. tim1 supports independent dma request generation. 3.19.2 general-purpose timers (timx) there are seven synchronizable general-purpose timers embedded in the stm32f401xb/stm32f401xc (see table 4 for differences). ? tim2, tim3, tim4, tim5 the stm32f401xb/stm32f401xc devices are 4 full-featured general-purpose timers: tim2, tim5, tim3, and tim4.the tim2 and tim5 timers are based on a 32-bit auto- reload up/downcounter and a 16-bit prescaler. the tim3 and tim4 timers are based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. they all feature four independent channels for input capture/output compare, pwm or one-pulse mode output. this gives up to 16 input capture/output compare/pwms on the largest packages. the tim2, tim3, tim4, tim5 general-purpose timers can work together, or with the other general-purpose timers and the advanc ed-control timers tim1 and tim8 via the timer link feature for synchronization or event chaining. any of these general-purpose timers can be used to generate pwm outputs. tim2, tim3, tim4, tim5 all have indepen dent dma request generation. they are capable of handling quadrature (incremental ) encoder signals and the digital outputs from 1 to 4 hall-effect sensors. ? tim9, tim10 and tim11 these timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. tim10 and tim11 feature one independent channel, whereas tim9 has two independent channels for input capture/output compare, pwm or one-pulse mode output. they can be synchronized with t he tim2, tim3, tim4, tim5 full-featured general-purpose timers. they can also be used as simple time bases. 3.19.3 independent watchdog the independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. it is clocked from an independent 32 khz internal rc and as it operates independently from the main clock, it can operate in stop and stan dby modes. it can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. it is hardware- or software-configurable through the option bytes. 3.19.4 window watchdog the window watchdog is based on a 7-bit downcounter that can be set as free-running. it can be used as a watchdog to reset the device when a problem occurs. it is clocked from the main clock. it has an early warning interrupt capab ility and the counter can be frozen in debug mode. docid024738 rev 6 28/135 stm32f401xb stm32f401xc functional overview 53 3.19.5 systick timer this timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. it features: ? a 24-bit downcounter ? autoreload capability ? maskable system interrupt generation when the counter reaches 0 ? programmable clock source. 3.20 inter-integrated circuit interface (i 2 c) up to three i 2 c bus interfaces can operate in multimaster and slave modes. they can support the standard (up to 100 khz) and fast (up to 400 khz) modes. the i2c bus frequency can be increased up to 1 mhz. for more details about the complete solution, please contact your local st sales representative.they also support the 7/10-bit addressing mode and the 7-bit dual addressing mode (as slave). a hardware crc generation/verification is embedded. they can be served by dma and they support smbus 2.0/pmbus. the devices also include programmable analog and digital noise filters (see table 5 ). 3.21 universal synchronous/asynch ronous receiver transmitters (usart) the devices embed three universal synchron ous/asynchronous receiver transmitters (usart1, usart2 and usart6). these three interfaces provide asynchronous communication, irda sir endec support, multiprocessor communication mode, single-wire half-duplex communication mode and have lin master/slave capability. the usart1 and u sart6 interfaces are able to communicate at speeds of up to 10.5 mbit/s. the usart2 interface communicates at up to 5.25 bit/s. usart1 and usart2 also provide hardware management of the cts and rts signals, smart card mode (iso 7816 compliant) and spi-like commu nication capability. all interfaces can be served by the dma controller. table 5. comparison of i2c analog and digital filters analog filter digital filter pulse width of suppressed spikes 50 ns programmable length from 1 to 15 i2c peripheral clocks functional overview stm32f401xb stm32f401xc 29/135 docid024738 rev 6 3.22 serial peripheral interface (spi) the devices feature up to four spis in slave and master modes in full-duplex and simplex communication modes. spi1 and spi4 can comm unicate at up to 42 mbit/s, spi2 and spi3 can communicate at up to 21 mbit/s. the 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. the hardware crc generation/verification supports basic sd card/mmc modes. all spis can be served by the dma controller. the spi interface can be configured to operat e in ti mode for comm unications in master mode and slave mode. 3.23 inter-integr ated sound (i 2 s) two standard i 2 s interfaces (multiplexed with spi2 and spi3) are available. they can be operated in master or slave mode, in full duplex and simplex communication modes and can be configured to operate with a 16-/32-bit resolution as an input or output channel. audio sampling frequencies from 8 khz up to 192 khz are supported. when either or both of the i 2 s interfaces is/are configured in master mo de, the master clock can be output to the external dac/codec at 256 ti mes the sampling frequency. all i 2 sx can be served by the dma controller. 3.24 audio pll (plli2s) the devices feature an additional dedicated pll for audio i 2 s application. it allows to achieve error-free i 2 s sampling clock accuracy withou t compromising on the cpu performance. the plli2s configuration can be modified to manage an i 2 s sample rate change without disabling the main pll (pll) used for the cpu. the audio pll can be programmed with very low error to obtain sampling rates ranging from 8 khz to 192 khz. in addition to the audio pll, a master clock input pin can be used to synchronize the i2s flow with an external pll (or codec output). table 6. usart feature comparison usart name standard features modem (rts/cts) lin spi master irda smartcard (iso 7816) max. baud rate in mbit/s (oversampling by 16) max. baud rate in mbit/s (oversampling by 8) apb mapping usart1 x x x x x x 5.25 10.5 apb2 (max. 84 mhz) usart2 x x x x x x 2.62 5.25 apb1 (max. 42 mhz) usart6 x n.a x x x x 5.25 10.5 apb2 (max. 84 mhz) docid024738 rev 6 30/135 stm32f401xb stm32f401xc functional overview 53 3.25 secure digital input/ output interface (sdio) an sd/sdio/mmc host interface is availabl e, that supports multimediacard system specification version 4.2 in three different da tabus modes: 1-bit (default), 4-bit and 8-bit. the interface allows data transfer at up to 48 mhz, and is compliant with the sd memory card specification version 2.0. the sdio card specification version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit. the current version supports only one sd/sdi o/mmc4.2 card at any one time and a stack of mmc4.1 or previous. in addition to sd/sdio/mmc, this interface is fully compliant with the ce-ata digital protocol rev1.1. 3.26 universal serial bus on -the-go full-speed (otg_fs) the devices embed an usb otg full-speed de vice/host/otg peripher al with integrated transceivers. the usb otg fs peripheral is compliant with the usb 2.0 specification and with the otg 1.0 specification. it has software-configurable endpoint setting and supports suspend/resume. the usb otg full-speed controller requires a dedicated 48 mhz clock that is generated by a pll connected to the hse oscillato r. the major features are: ? combined rx and tx fifo size of 320 35 bits with dynamic fifo sizing ? supports the session request protocol (srp) and host negotiation protocol (hnp) ? 4 bidirectional endpoints ? 8 host channels with periodic out support ? hnp/snp/ip inside (no need for any external resistor) ? for otg/host modes, a power switch is needed in case bus-powered devices are connected 3.27 general-purpose in put/outputs (gpios) each of the gpio pins can be configured by so ftware as output (push-pull or open-drain, with or without pull-up or pull-down), as input (f loating, with or without pull-up or pull-down) or as peripheral alternate function. most of the gpio pins are shared with digital or analog alternate functions. all gpios are high-current -capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission. the i/o configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the i/os registers. fast i/o handling allowing maximum i/o toggling up to 84 mhz. 3.28 analog-to-digita l converter (adc) one 12-bit analog-to-digital converter is embedded and shares up to 16 external channels, performing conversions in the single-sho t or scan mode. in scan mode, automatic conversion is performed on a selected group of analog inputs. functional overview stm32f401xb stm32f401xc 31/135 docid024738 rev 6 the adc can be served by the dma controller. an analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. an interrupt is generated when the converted vo ltage is outside the programmed thresholds. to synchronize a/d conversion and timers, t he adcs could be triggered by any of tim1, tim2, tim3, tim4 or tim5 timer. 3.29 temperature sensor the temperature sensor has to generate a voltage that varies linearly with temperature. the conversion range is between 1.7 v and 3.6 v. the temperature sensor is internally connected to the adc_in18 input channel wh ich is used to convert the sensor output voltage into a digital value. refer to the reference manual for additional information. as the offset of the temperature sensor varies fr om chip to chip due to process variation, the internal temperature sensor is mainly suitab le for applications that detect temperature changes instead of absolute temperatures. if an accurate temperature reading is needed, then an external temperature sensor part should be used. 3.30 serial wire jtag debug port (swj-dp) the arm swj-dp interface is embedded, and is a combined jtag and serial wire debug port that enables either a serial wire debug or a jtag probe to be connected to the target. debug is performed using 2 pins only instead of 5 required by the jtag (jtag pins could be re-use as gpio with alternate function): the jtag tms and tck pins are shared with swdio and swclk, respectively, and a specific sequence on the tms pin is used to switch between jtag-dp and sw-dp. 3.31 embedded trace macrocell? the arm embedded trace macrocell provides a greater visibility of the instruction and data flow inside the cpu core by streaming compressed data at a very high rate from the stm32f401xb/stm32f401xc through a small number of etm pins to an external hardware trace port analyzer (tpa) device. the tpa is connected to a host computer using any high-speed channel available. real-time in struction and data flow activity can be recorded and then formatted for display on the host computer that runs the debugger software. tpa hardware is commercially available from common development tool vendors. the embedded trace macrocell operates wi th third party debugger software tools. docid024738 rev 6 32/135 stm32f401xb stm32f401xc pinouts and pin description 53 4 pinouts and pin description figure 10. stm32f401xb/stm32f401xc wlcsp49 pinout 1. the above figure shows the package top view. 0 6 9 $ % ( ' & ) * 9 ' ' 3 & 2 6 & b , 1 9 % $ 7 3 + 2 6 & b , 1 1 5 6 7 9 ' ' $ 9 5 ( ) 3 $ 9 6 6 3 ' 5 b 2 1 3 & 2 6 & b 2 8 7 9 6 6 $ 9 5 ( ) 3 $ 3 $ % 2 2 7 3 % 3 + 2 6 & b 2 8 7 3 % 3 % 3 % 3 % 3 % 3 $ 3 $ 9 ' ' 3 $ 9 6 6 3 $ 3 % 3 $ 3 % 3 $ 9 & $ 3 b 3 $ 3 % 9 ' ' 9 6 6 3 % 3 $ 3 $ 3 % 3 % 3 % 3 % 3 & 3 $ 3 $ 3 $ 3 $ 3 % pinouts and pin description stm32f401xb stm32f401xc 33/135 docid024738 rev 6 figure 11. stm32f401xb/stm32f401xc ufqfpn48 pinout 1. the above figure shows the package top view. 0 6 9 9 6 6 % 2 2 7 3 % 3 % 3 % 3 % 3 % 3 $ 3 $ 9 ' ' 9 6 6 3 $ 8 ) 4 ) 3 1 3 $ 9 6 6 $ 9 5 ( ) 3 $ 9 ' ' $ 9 5 ( ) 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 9 ' ' 3 $ 3 $ 3 $ 3 $ 3 $ 3 % 3 % 3 % 9 6 6 3 % 9 & $ 3 b 3 % 3 % 3 % 3 % 9 % $ 7 3 & 3 & 2 6 & b , 1 3 + 2 6 & b , 1 1 5 6 7 3 % 3 % 9 ' ' 3 & 2 6 & b 2 8 7 3 + 2 6 & b 2 8 7 docid024738 rev 6 34/135 stm32f401xb stm32f401xc pinouts and pin description 53 figure 12. stm32f401xb/stm32f401xc lqfp64 pinout 1. the above figure shows the package top view. 9 % $ 7 3 & 2 6 & b , 1 3 + 2 6 & b , 1 1 5 6 7 3 & 3 & 3 & 3 & 9 6 6 $ 9 5 ( ) 9 ' ' $ 9 5 ( ) 3 $ 3 $ 3 $ 9 ' ' 3 % 3 % % 2 2 7 3 % 3 % 3 % 3 % 3 % 3 ' 3 & 3 & 3 & 3 $ 3 $ 9 ' ' 9 6 6 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 & 3 & 3 & 3 & 3 % 3 % 3 % 3 % 3 $ 9 6 6 3 $ 3 $ 3 $ 3 $ 3 & 3 & 3 % 3 % 3 % 3 % 9 & $ 3 b / 4 ) 3 3 & 0 6 9 9 ' ' 9 6 6 9 ' ' 9 6 6 3 + 2 6 & b 2 8 7 3 & 2 6 & b 2 8 7 pinouts and pin description stm32f401xb stm32f401xc 35/135 docid024738 rev 6 figure 13. stm32f401xb/st m32f401xc lqfp100 pinout 1. the above figure shows the package top view. 0 % 0 % 0 % 0 % 0 % 6 " ! 4 0 # / 3 # ? ) . 0 # / 3 # ? / 5 4 6 3 3 6 $ $ 0 ( / 3 # ? ) . . 2 3 4 0 # 0 # 0 # 0 # 6 $ $ 6 3 3 ! 6 2 % & 6 $ $ ! 6 2 % & 0 ! 0 ! 0 ! 6 $ $ 6 3 3 6 # ! 0 ? 0 ! 0 ! 0 ! 0 ! 0 ! 0 ! 0 # 0 # 0 # 0 # 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 " 0 " 0 " 0 " 0 ! 6 3 3 6 $ $ 0 ! 0 ! 0 ! 0 ! 0 # 0 # 0 " 0 " 0 " 0 % 0 % 0 % 0 % 0 % 0 % 0 % 0 % 0 % 0 " 6 # ! 0 ? 6 3 3 6 $ $ 6 $ $ 6 3 3 0 % 0 % 0 " 0 " " / / 4 0 " 0 " 0 " 0 " 0 " 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 # 0 # 0 # 0 ! 0 ! - 3 6 , 1 & 0 0 # 0 ( / 3 # ? / 5 4 docid024738 rev 6 36/135 stm32f401xb stm32f401xc pinouts and pin description 53 figure 14. stm32f401xb/stm32f401xc ufbga100 pinout 1. this figure shows the package top view 0 6 9 $ % ( ' & ) * + - . / 0 3 ( 2 6 & b , 1 3 & 2 6 & b 2 8 7 3 & 3 & $ 1 7 , b 7 $ 0 3 3 ( 2 6 & b 2 8 7 3 & 9 6 6 $ 9 5 ( ) 9 5 ( ) 9 ' ' $ 3 ( 3 ( 3 ( 3 ( 9 % $ 7 9 6 6 9 ' ' 1 5 6 7 3 & 3 & 3 $ : . 8 3 3 $ 3 % 3 ( 3 % 9 6 6 % < 3 $ 6 6 b 5 ( * 3 ' 5 b 2 1 3 & 3 $ 3 $ 3 $ % 2 2 7 3 % 9 ' ' 3 $ 3 $ 3 $ 3 ' 3 % 3 % 3 & 3 & 3 % 3 ' 3 ' 3 % 3 % 3 % 3 ' 3 ( 3 ( 3 % 3 ' 3 ' 3 ' 3 ( 3 ( 3 $ 3 ' 3 ' 3 % 3 ( 3 ( 3 $ 3 & 3 & 3 & 3 $ 3 ' 3 ' 3 % 3 % 3 ( 3 $ 3 & 9 & $ 3 b 3 $ 3 & 3 ' 3 ' 3 % 9 & $ 3 b 3 ( 9 6 6 9 ' ' 3 $ 3 $ 3 $ 3 & 3 & 3 ' 3 ' 3 % 3 % 3 ( 9 6 6 9 ' ' 3 + 3 + 2 6 & b , 1 pinouts and pin description stm32f401xb stm32f401xc 37/135 docid024738 rev 6 table 7. legend/abbreviations used in the pinout table name abbreviation definition pin name unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name pin type s supply pin i input only pin i/o input/ output pin i/o structure ft 5 v tolerant i/o b dedicated boot0 pin nrst bidirectional reset pin with embedded weak pull-up resistor notes unless otherwise specified by a note, all i/os are set as floating inputs during and after reset alternate functions functions selected through gpiox_afr registers additional functions functions directly selected/enabl ed through peripheral registers table 8. stm32f401xb/stm32f401xc pin definitions pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions uqfn48 wlcsp49 lqfp64 lqfp100 ufbga100 - - - 1 b2 pe2 i/o ft - spi4_sck, traceclk, eventout - - - - 2 a1 pe3 i/o ft - traced0, eventout - - - - 3 b1 pe4 i/o ft - spi4_nss, traced1, eventout - - - - 4 c2 pe5 i/o ft - spi4_miso, tim9_ch1, traced2, eventout - - - - 5 d2 pe6 i/o ft - spi4_mosi, tim9_ch2, traced3, eventout - - - - - d3 vss s - - - - ----c4 vdd s- - - - 1 b7 1 6 e2 vbat s - - - - 2 d5 2 7 c1 pc13 i/o ft (2) (3) eventout, rtc_tamp1, rtc_out, rtc_ts docid024738 rev 6 38/135 stm32f401xb stm32f401xc pinouts and pin description 53 3c73 8 d1 pc14- osc32_in (pc14) i/o ft (2) (3) (4) eventout osc32_in 4c64 9 e1 pc15- osc32_out (pc15) i/o ft (2) (3) (4) eventout osc32_out - - - 10 f2 vss s - - - - ---11g2 vdd s- - - - 5d75 12f1 ph0-osc_in (ph0) i/o ft (4) eventout osc_in 6d66 13g1 ph1- osc_out (ph1) i/o ft (4) eventout osc_out 7 e7 7 14 h2 nrst i/o ft - eventout - - - 8 15 h1 pc0 i/o ft - eventout adc1_in10 - - 9 16 j2 pc1 i/o ft - eventout adc1_in11 - - 10 17 j3 pc2 i/o ft - spi2_miso, i2s2ext_sd, eventout adc1_in12 - - 11 18 k2 pc3 i/o ft - spi2_mosi/i2s2_sd, eventout adc1_in13 ---19- vdd s- - - - 8 e6 12 20 - vssa/vref- s - - - - - - - - j1 vssa s - - - - - - - - k1 vref- s - - - - 9 - 13 - - vdda/vref+ s - - - - ---21l1 vref+ s- - - - - f7 - 22 m1 vdda s - - - - 10 f6 14 23 l2 pa0 i/o ft (5) usart2_cts, tim2_ch1/tim2_etr, tim5_ch1, eventout adc1_in0, wkup 11 g7 15 24 m2 pa1 i/o ft - usart2_rts, tim2_ch2, tim5_ch2, eventout adc1_in1 12 e5 16 25 k3 pa2 i/o ft - usart2_tx, tim2_ch3, tim5_ch3, tim9_ch1, eventout adc1_in2 table 8. stm32f401xb/stm32f401x c pin definitions (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions uqfn48 wlcsp49 lqfp64 lqfp100 ufbga100 pinouts and pin description stm32f401xb stm32f401xc 39/135 docid024738 rev 6 13 e4 17 26 l3 pa3 i/o ft - usart2_rx, tim2_ch4, tim5_ch4, tim9_ch2, eventout adc1_in3 - - 18 27 - vss s - - - - - - 19 28 - vdd s - - - - ----e3 bypass_ reg ift - - - 14 g6 20 29 m3 pa4 i/o ft - spi1_nss, spi3_nss/i2s3_ws, usart2_ck, eventout adc1_in4 15 f5 21 30 k4 pa5 i/o ft - spi1_sck, tim2_ch1/tim2_etr, eventout adc1_in5 16 f4 22 31 l4 pa6 i/o ft - spi1_miso, tim1_bkin, tim3_ch1, eventout adc1_in6 17 f3 23 32 m4 pa7 i/o ft - spi1_mosi, tim1_ch1n, tim3_ch2, eventout adc1_in7 - - 24 33 k5 pc4 i/o ft - eventout adc1_in14 - - 25 34 l5 pc5 i/o ft - eventout adc1_in15 18 g5 26 35 m5 pb0 i/o ft - tim1_ch2n, tim3_ch3, eventout adc1_in8 19 g4 27 36 m6 pb1 i/o ft - tim1_ch3n, tim3_ch4, eventout adc1_in9 20 g3 28 37 l6 pb2 i/o ft - eventout boot1 - - - 38 m7 pe7 i/o ft - tim1_etr, eventout - - - - 39 l7 pe8 i/o ft - tim1_ch1n, eventout - - - - 40 m8 pe9 i/o ft - tim1_ch1, eventout - - - - 41 l8 pe10 i/o ft - tim1_ch2n, eventout - - - - 42 m9 pe11 i/o ft - spi4_nss, tim1_ch2, eventout - - - - 43 l9 pe12 i/o ft - spi4_sck, tim1_ch3n, eventout - - - - 44 m10 pe13 i/o ft - spi4_miso, tim1_ch3, eventout - table 8. stm32f401xb/stm32f401x c pin definitions (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions uqfn48 wlcsp49 lqfp64 lqfp100 ufbga100 docid024738 rev 6 40/135 stm32f401xb stm32f401xc pinouts and pin description 53 - - - 45 m11 pe14 i/o ft - spi4_mosi, tim1_ch4, eventout - - - - 46 m12 pe15 i/o ft - tim1_bkin, eventout - 21 e3 29 47 l10 pb10 i/o ft - spi2_sck/i2s2_ck, i2c2_scl, tim2_ch3, eventout - - - - - k9 pb11 i/o ft - tim2_ch4, i2c2_sda, eventout - 22 g2 30 48 l11 vcap_1 s - - - - 23 d3 31 49 f12 vss s - - - - 24 f2 32 50 g12 vdd s - - - - 25 e2 33 51 l12 pb12 i/o ft - spi2_nss/i2s2_ws, i2c2_smba, tim1_bkin, eventout - 26 g1 34 52 k12 pb13 i/o ft - spi2_sck/i2s2_ck, tim1_ch1n, eventout - 27 f1 35 53 k11 pb14 i/o ft - spi2_miso, i2s2ext_sd, tim1_ch2n, eventout - 28 e1 36 54 k10 pb15 i/o ft - spi2_mosi/i2s2_sd, tim1_ch3n, eventout rtc_refin - - - 55 - pd8 i/o ft - eventout - - - - 56 k8 pd9 i/o ft - eventout - - - - 57 j12 pd10 i/o ft - eventout - - - - 58 j11 pd11 i/o ft - eventout - - - - 59 j10 pd12 i/o ft - tim4_ch1, eventout - - - - 60 h12 pd13 i/o ft - tim4_ch2, eventout - - - - 61 h11 pd14 i/o ft - tim4_ch3, eventout - - - - 62 h10 pd15 i/o ft - tim4_ch4, eventout - - - 37 63 e12 pc6 i/o ft - i2s2_mck, usart6_tx, tim3_ch1, sdio_d6, eventout - - - 38 64 e11 pc7 i/o ft - i2s3_mck, usart6_rx, tim3_ch2, sdio_d7, eventout - table 8. stm32f401xb/stm32f401x c pin definitions (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions uqfn48 wlcsp49 lqfp64 lqfp100 ufbga100 pinouts and pin description stm32f401xb stm32f401xc 41/135 docid024738 rev 6 - - 39 65 e10 pc8 i/o ft - usart6_ck, tim3_ch3, sdio_d0, eventout - - - 40 66 d12 pc9 i/o ft - i2s_ckin, i2c3_sda, tim3_ch4, sdio_d1, mco_2, eventout - 29 d1 41 67 d11 pa8 i/o ft - i2c3_scl, usart1_ck, tim1_ch1, otg_fs_sof, mco_1, eventout - 30 d2 42 68 d10 pa9 i/o ft - i2c3_smba, usart1_tx, tim1_ch2, eventout otg_fs_vbus 31 c2 43 69 c12 pa10 i/o ft - usart1_rx, tim1_ch3, otg_fs_id, eventout - 32 c1 44 70 b12 pa11 i/o ft - usart1_cts, usart6_tx, tim1_ch4, otg_fs_dm, eventout - 33 c3 45 71 a12 pa12 i/o ft - usart1_rts, usart6_rx, tim1_etr, otg_fs_dp, eventout - 34 b3 46 72 a11 pa13 (jtms- swdio) i/o ft - jtms-swdio, eventout - - - - 73 c11 vcap_2 s - - - - 35 b1 47 74 f11 vss s - - - - 36 - 48 75 g11 vdd s - - - - -b2- - - vdd s - - - - 37 a1 49 76 a10 pa14 (jtck- swclk) i/o ft - jtck-swclk, eventout - 38 a2 50 77 a9 pa15 (jtdi) i/o ft - jtdi, spi1_nss, spi3_nss/i2s3_ws, tim2_ch1/tim2_etr, jtdi, eventout - - - 51 78 b11 pc10 i/o ft - spi3_sck/i2s3_ck, sdio_d2, eventout - - - 52 79 c10 pc11 i/o ft - i2s3ext_sd, spi3_miso, sdio_d3, eventout - - - 53 80 b10 pc12 i/o ft - spi3_mosi/i2s3_sd, sdio_ck, eventout - - - - 81 c9 pd0 i/o ft - eventout - table 8. stm32f401xb/stm32f401x c pin definitions (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions uqfn48 wlcsp49 lqfp64 lqfp100 ufbga100 docid024738 rev 6 42/135 stm32f401xb stm32f401xc pinouts and pin description 53 - - - 82 b9 pd1 i/o ft - eventout - - - 54 83 c8 pd2 i/o ft - tim3_etr, sdio_cmd, eventout - - - - 84 b8 pd3 i/o ft - spi2_sck/i2s2_ck, usart2_cts, eventout - - - - 85 b7 pd4 i/o ft - usart2_rts, eventout - - - - 86 a6 pd5 i/o ft - usart2_tx, eventout - - - - 87 b6 pd6 i/o ft - spi3_mosi/i2s3_sd, usart2_rx, eventout - - - - 88 a5 pd7 i/o ft - usart2_ck, eventout - 39 a3 55 89 a8 pb3 (jtdo-swo) i/o ft - jtdo-swo, spi1_sck, spi3_sck/i2s3_ck, i2c2_sda, tim2_ch2, eventout - 40 a4 56 90 a7 pb4 (njtrst) i/o ft - njtrst, spi1_miso, spi3_miso, i2s3ext_sd, i2c3_sda, tim3_ch1, eventout - 41 b4 57 91 c5 pb5 i/o ft - spi1_mosi, spi3_mosi/i2s3_sd, i2c1_smba, tim3_ch2, eventout - 42 c4 58 92 b5 pb6 i/o ft - i2c1_scl, usart1_tx, tim4_ch1, eventout - 43 d4 59 93 b4 pb7 i/o ft - i2c1_sda, usart1_rx, tim4_ch2, eventout - 44 a5 60 94 a4 boot0 i b - - v pp 45 b5 61 95 a3 pb8 i/o ft - i2c1_scl, tim4_ch3, tim10_ch1, sdio_d4, eventout - 46 c5 62 96 b3 pb9 i/o ft - spi2_nss/i2s2_ws, i2c1_sda, tim4_ch4, tim11_ch1, sdio_d5, eventout - - - - 97 c3 pe0 i/o ft - tim4_etr, eventout - - - - 98 a2 pe1 i/o ft - eventout - table 8. stm32f401xb/stm32f401x c pin definitions (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions uqfn48 wlcsp49 lqfp64 lqfp100 ufbga100 pinouts and pin description stm32f401xb stm32f401xc 43/135 docid024738 rev 6 47 a6 63 99 - vss s - - - - - b6 - - h3 pdr_on i ft - - - 48 a7 64 100 - vdd s - - - - 1. function availability depends on the chosen device. 2. pc13, pc14 and pc15 are supplied through the power switch. si nce the switch only sinks a limited amount of current (3 ma), the use of gpios pc13 to pc15 in output mode is limited: - the speed should not exceed 2 mhz with a maximum load of 30 pf. - these i/os must not be used as a current source (e.g. to drive an led). 3. main function after the first backup domain power-up. later on, it depends on the contents of the rtc registers even after reset (because these registers are not reset by the main reset) . for details on how to manage these i/os, refer to the rtc register description sections in the stm32f401xx reference manual. 4. ft = 5 v tolerant except when in analog mode or oscillator mode (for pc14, pc15, ph0 and ph1). 5. if the device is delivered in an ufbga100 and the bypass_reg pi n is set to vdd (regulator off/internal reset on mode), then pa0 is used as an internal reset (active low) table 8. stm32f401xb/stm32f401x c pin definitions (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions uqfn48 wlcsp49 lqfp64 lqfp100 ufbga100 pinouts and pin description stm32f401xb stm32f401xc 44/135 docid024738 rev 6 table 9. alternate function mapping port af00 af01 af02 af03 af04 af05 af06 af07 af08 af09 af10 af11 af12 af13 af14 af15 sys_af tim1/tim2 tim3/ tim4/ tim5 tim9/ tim10/ tim11 i2c1/i2c2/ i2c3 spi1/spi2/ i2s2/spi3/ i2s3/spi4 spi2/i2s2/ spi3/ i2s3 spi3/i2s3/ usart1/ usart2 usart6 i2c2/ i2c3 otg1_fs sdio port a pa0 - tim2_ch1/ tim2_etr tim5_ch1 - - - - usart2_ cts -- ----- event out pa1 - tim2_ch2 tim5_ch2 - - - - usart2_ rts -- ----- event out pa2 - tim2_ch3 tim5_ch3 tim9_ch1 - - - usart2_ tx -- ----- event out pa3 - tim2_ch4 tim5_ch4 tim9_ch2 - - usart2_ rx -- ----- event out pa4 - - - - - spi1_nss spi3_nss/ i2s3_ws usart2_ ck -- ----- event out pa5 - tim2_ch1/ tim2_etr ---spi1_sck- -------- event out pa6 - tim1_bkin tim3_ch1 - - spi1_ miso --------- event out pa7 - tim1_ch1n tim3_ch2 - - spi1_ mosi ------ - - - event out pa8 mco_1 tim1_ch1 - - i2c3_scl - - usart1_ ck -- otg_fs_ sof - - - - event out pa9 - tim1_ch2 - - i2c3_ smba -- usart1_ tx -- otg_fs_ vbus ----- event out pa10 - tim1_ch3 - - - - - usart1_ rx -- otg_fs_i d ---- event out pa11 - tim1_ch4 - - - - - usart1_ cts usart6_ tx - otg_fs_ dm ---- event out pa12 - tim1_etr - - - - - usart1_ rts usart6_ rx - otg_fs_ dp ---- event out pa13 jtms_ swdio ----- - -------- event out pa14 jtck_ swclk ----- - -------- event out pa15 jtdi tim2_ch1/ tim2_etr ---spi1_nss spi3_nss/ i2s3_ws --- ----- event out stm32f401xb stm32f401xc pinouts and pin description docid024738 rev 6 45/135 port b pb0 - tim1_ch2n tim3_ch3 - - - - - - - - - - - - event out pb1 - tim1_ch3n tim3_ch4 - - - - - - - - - - - - event out pb2 - - - - - - - - - - - - - - - event out pb3 jtdo- swo tim2_ch2 - - - spi1_sck spi3_sck/ i2s3_ck - - i2c2_sda - - - - - event out pb4 jtrst - tim3_ch1 - - spi1_ miso spi3_miso i2s3ext_s d -i2c3_sda - - - -- event out pb5 - - tim3_ch2 - i2c1_ smba spi1 _mosi spi3_mosi/ i2s3_sd --- ----- event out pb6 - - tim4_ch1 - i2c1_scl - - usart1_ tx -- ----- event out pb7 - - tim4_ch2 - i2c1_sda - - usart1_ rx -- ----- event out pb8 - - tim4_ch3 tim10_ch1 i2c1_scl - - - - - - - sdio_ d4 -- event out pb9 - - tim4_ch4 tim11_ch1 i2c1_sda spi2_nss/i 2s2_ws ------ sdio_ d5 -- event out pb10 - tim2_ch3 - - i2c2_scl spi2_sck/i 2s2_ck --------- event out pb11 - tim2_ch4 - - i2c2_sda - - - - - - - - - - event out pb12 - tim1_bkin - - i2c2_ smba spi2_nss/i 2s2_ws --------- event out pb13 - tim1_ch1n - - - spi2_sck/i 2s2_ck --------- event out pb14 - tim1_ch2n - - - spi2_miso i2s2ext_sd - - - - - - - - event out pb15 rtc_ refn tim1_ch3n - - - spi2_mosi /i2s2_sd --------- event out table 9. alternate function mapping (continued) port af00 af01 af02 af03 af04 af05 af06 af07 af08 af09 af10 af11 af12 af13 af14 af15 sys_af tim1/tim2 tim3/ tim4/ tim5 tim9/ tim10/ tim11 i2c1/i2c2/ i2c3 spi1/spi2/ i2s2/spi3/ i2s3/spi4 spi2/i2s2/ spi3/ i2s3 spi3/i2s3/ usart1/ usart2 usart6 i2c2/ i2c3 otg1_fs sdio pinouts and pin description stm32f401xb stm32f401xc 46/135 docid024738 rev 6 port c pc0 - - - - - - - - - - - - - - - event out pc1 - - - - - - - - - - - - - - - event out pc2 - - - - - spi2_ miso i2s2ext_sd - - - - - - - - event out pc3 - - - - - spi2_mosi /i2s2_sd --------- event out pc4 - - - - - - - - - - - - - - - event out pc5 - - - - - - - - - - - - - - - event out pc6 - -- tim3_ch1 - - i2s2_mck - - usart6_ tx --- sdio_ d6 -- event out pc7 - tim3_ch2 - - - i2s3_mck - usart6_ rx --- sdio_ d7 -- event out pc8 - - tim3_ch3 - - - - - usart6_ ck --- sdio_ d0 -- event out pc9 mco_2 - tim3_ch4 - i2c3_sda i2s_ckin - - - - - - sdio_ d1 -- event out pc10 - - - - - - spi3_sck/ i2s3_ck --- -- sdio_ d2 -- event out pc11 - - - - - i2s3ext_ sd spi3_miso - - - - - sdio_ d3 -- event out pc12 - - - - - - spi3_mosi/ i2s3_sd --- -- sdio_ ck -- event out pc13 - - - - - - - - - - - - - - - event out pc14 - - - - - - - - - - - - - - - event out pc15 - - - - - - - - - - - - - - - event out table 9. alternate function mapping (continued) port af00 af01 af02 af03 af04 af05 af06 af07 af08 af09 af10 af11 af12 af13 af14 af15 sys_af tim1/tim2 tim3/ tim4/ tim5 tim9/ tim10/ tim11 i2c1/i2c2/ i2c3 spi1/spi2/ i2s2/spi3/ i2s3/spi4 spi2/i2s2/ spi3/ i2s3 spi3/i2s3/ usart1/ usart2 usart6 i2c2/ i2c3 otg1_fs sdio stm32f401xb stm32f401xc pinouts and pin description docid024738 rev 6 47/135 port d pd0 - - - - - - - - - - - - - - - event out pd1 - - - - - - - - - - - - - - - event out pd2 - - tim3_etr - - - - - - - - - sdio_ cmd -- event out pd3 - - - - - spi2_sck/ i2s2_ck - usart2_ cts -- - - - - - - event out pd4 - - - - - - - usart2_ rts ------ event out pd5 - - - - - - - usart2_ tx -- ----- event out pd6 - - - - - spi3_mosi /i2s3_sd - usart2_ rx -- ----- event out pd7 - - - - - - - usart2_ ck -- ----- event out pd8 - - - - - - - - - - - - - - - event out pd9 - - - - - - - - - - - - - - - event out pd10 - - - - - - - - - - - - - - - event out pd11 - - - - - - - - - - - - - - - event out pd12 - - tim4_ch1 - - - - - - - - - - - - event out pd13 - - tim4_ch2 - - - - - - - - - - - - event out pd14 - - tim4_ch3 - - - - - - - - - - - - event out pd15 - - tim4_ch4 - - - - - - - - - - - - event out table 9. alternate function mapping (continued) port af00 af01 af02 af03 af04 af05 af06 af07 af08 af09 af10 af11 af12 af13 af14 af15 sys_af tim1/tim2 tim3/ tim4/ tim5 tim9/ tim10/ tim11 i2c1/i2c2/ i2c3 spi1/spi2/ i2s2/spi3/ i2s3/spi4 spi2/i2s2/ spi3/ i2s3 spi3/i2s3/ usart1/ usart2 usart6 i2c2/ i2c3 otg1_fs sdio pinouts and pin description stm32f401xb stm32f401xc 48/135 docid024738 rev 6 port e pe0 - - tim4_etr - - - - - - - - - - - - event out pe1 - tim1_ch2n - - - - - - - - - - - - - event out pe2 tracecl k ----spi4_sck- -------- event out pe3 traced0 - - - - - - - - - - - - - - event out pe4 traced1 - - - - spi4_nss - - - - - - - - - event out pe5 traced2 - - tim9_ch1 - spi4_miso - - - - - - - - - event out pe6 traced3 - - tim9_ch2 - spi4_mosi - - - - - - - - - event out pe7 - tim1_etr - - - - - - - - - - - - - event out pe8 - tim1_ch1n - - - - - - - - - - - - - event out pe9 - tim1_ch1 - - - - - - - - - - - - - event out pe10 - tim1_ch2n - - - - - - - - - - - - - event out pe11 - tim1_ch2 - - - spi4_nss - - - - - - - - - event out pe12 - tim1_ch3n - - - spi4_sck - - - - - - - - - event out pe13 - tim1_ch3 - - - spi4_miso - - - - - - - - - event out pe14 - tim1_ch4 - - - spi4_mosi - - - - - - - - - event out pe15 - tim1_bkin - - - - - - - - - - - - - event out table 9. alternate function mapping (continued) port af00 af01 af02 af03 af04 af05 af06 af07 af08 af09 af10 af11 af12 af13 af14 af15 sys_af tim1/tim2 tim3/ tim4/ tim5 tim9/ tim10/ tim11 i2c1/i2c2/ i2c3 spi1/spi2/ i2s2/spi3/ i2s3/spi4 spi2/i2s2/ spi3/ i2s3 spi3/i2s3/ usart1/ usart2 usart6 i2c2/ i2c3 otg1_fs sdio stm32f401xb stm32f401xc pinouts and pin description docid024738 rev 6 49/135 port h ph0 - - - - - - - - - - - - - - - event out ph1 - - - - - - - - - - - - - - - event out table 9. alternate function mapping (continued) port af00 af01 af02 af03 af04 af05 af06 af07 af08 af09 af10 af11 af12 af13 af14 af15 sys_af tim1/tim2 tim3/ tim4/ tim5 tim9/ tim10/ tim11 i2c1/i2c2/ i2c3 spi1/spi2/ i2s2/spi3/ i2s3/spi4 spi2/i2s2/ spi3/ i2s3 spi3/i2s3/ usart1/ usart2 usart6 i2c2/ i2c3 otg1_fs sdio docid024738 rev 6 50/135 stm32f401xb stm32f401xc memory mapping 53 5 memory mapping the memory map is shown in figure 15 . figure 15. memory map 0 e \ w h e o r f n & r u w h [ 0 v l q w h u q d o s h u l s k h u d o v 0 e \ w h e o r f n 1 r w x v h g 0 e \ w h e o r f n 3 h u l s k h u d o v 0 e \ w h e o r f n 6 5 $ 0 [ [ ) ) ) ) ) ) ) [ [ ) ) ) ) ) ) ) [ [ ) ) ) ) ) ) ) [ [ & [ ' ) ) ) ) ) ) ) [ ( [ ) ) ) ) ) ) ) ) 0 e \ w h e o r f n & r g h [ [ ) ) ) ) ) ) ) [ 5 h v h u y h g [ ) ) [ [ ) ) ) ) [ [ [ ' ) ) ) ) ) ) ) 0 6 9 $ + % 5 h v h u y h g [ ) ) ) ) [ 6 5 $ 0 . % d o l d v h g e \ e l w e d q g l q j [ [ ) ) ) ) $ 3 % $ 3 % [ % ) ) [ & [ ) ) ) ) 5 h v h u y h g [ [ ) ) ) ) ) ) ) [ ) ) $ + % 5 h v h u y h g ) o d v k p h p r u \ [ [ ) ) ( ) ) ) ) [ ) ) ) & [ ) ) ) & [ [ ) ) ) ) [ [ ) ) ) ) ) ) [ [ ) ) ) ) 5 h v h u y h g 5 h v h u y h g $ o l d v h g w r ) o d v k v \ v w h p p h p r u \ r u 6 5 $ 0 g h s h q g l q j r q w k h % 2 2 7 s l q v 6 \ v w h p p h p r u \ [ ) ) ) & [ ) ) ) ) ) ) ) [ ) ) ) $ [ ) ) ) % ) ) ) [ ) ) ) [ ) ) ) $ ) 2 s w l r q e \ w h v [ & r u w h [ 0 l q w h u q d o s h u l s k h u d o v [ ( [ ( ) ) ) ) ) 5 h v h u y h g [ ( [ ) ) ) ) ) ) ) ) 5 h v h u y h g [ % ) ) ) ) ) ) ) 5 h v h u y h g 5 h v h u y h g 5 h v h u y h g memory mapping stm32f401xb stm32f401xc 51/135 docid024738 rev 6 table 10. stm32f401xb/stm32f401xc register boundary addresses bus boundary address peripheral 0xe010 0000 - 0xffff ffff reserved cortex ? -m4 0xe000 0000 - 0xe00f ffff cortex-m4 internal peripherals 0x5004 0000 - 0xdfff ffff reserved ahb2 0x5000 0000 - 0x5003 ffff usb otg fs ahb1 0x4002 6800 - 0x4fff ffff reserved 0x4002 6400 - 0x4002 67ff dma2 0x4002 6000 - 0x4002 63ff dma1 0x4002 5000 - 0x4002 4fff reserved 0x4002 3c00 - 0x4002 3fff flash interface register 0x4002 3800 - 0x4002 3bff rcc 0x4002 3400 - 0x4002 37ff reserved 0x4002 3000 - 0x4002 33ff crc 0x4002 2000 - 0x4002 2fff reserved 0x4002 1c00 - 0x4002 1fff gpioh 0x4002 1400 - 0x4002 1bff reserved 0x4002 1000 - 0x4002 13ff gpioe 0x4002 0c00 - 0x4002 0fff gpiod 0x4002 0800 - 0x4002 0bff gpioc 0x4002 0400 - 0x4002 07ff gpiob 0x4002 0000 - 0x4002 03ff gpioa docid024738 rev 6 52/135 stm32f401xb stm32f401xc memory mapping 53 apb2 0x4001 4c00- 0x4001 ffff reserved 0x4001 4800 - 0x4001 4bff tim11 0x4001 4400 - 0x4001 47ff tim10 0x4001 4000 - 0x4001 43ff tim9 0x4001 3c00 - 0x4001 3fff exti 0x4001 3800 - 0x4001 3bff syscfg 0x4001 3400 - 0x4001 37ff spi4/i2s4 0x4001 3000 - 0x4001 33ff spi1 0x4001 2c00 - 0x4001 2fff sdio 0x4001 2400 - 0x4001 2bff reserved 0x4001 2000 - 0x4001 23ff adc1 0x4001 1800 - 0x4001 1fff reserved 0x4001 1400 - 0x4001 17ff usart6 0x4001 1000 - 0x4001 13ff usart1 0x4001 0800 - 0x4001 0fff reserved 0x4001 0400 - 0x4001 07ff tim8 0x4001 0000 - 0x4001 03ff tim1 0x4000 7400 - 0x4000 ffff reserved table 10. stm32f401xb/stm32f401xc register boundary addresses (continued) bus boundary address peripheral memory mapping stm32f401xb stm32f401xc 53/135 docid024738 rev 6 apb1 0x4000 7000 - 0x4000 73ff pwr 0x4000 6000 - 0x4000 6fff reserved 0x4000 5c00 - 0x4000 5fff i2c3 0x4000 5800 - 0x4000 5bff i2c2 0x4000 5400 - 0x4000 57ff i2c1 0x4000 4800 - 0x4000 53ff reserved 0x4000 4400 - 0x4000 47ff usart2 0x4000 4000 - 0x4000 43ff i2s3ext 0x4000 3c00 - 0x4000 3fff spi3 / i2s3 0x4000 3800 - 0x4000 3bff spi2 / i2s2 0x4000 3400 - 0x4000 37ff i2s2ext 0x4000 3000 - 0x4000 33ff iwdg 0x4000 2c00 - 0x4000 2fff wwdg 0x4000 2800 - 0x4000 2b ff rtc & bkp registers 0x4000 1000 - 0x4000 27ff reserved 0x4000 0c00 - 0x4000 0fff tim5 0x4000 0800 - 0x4000 0bff tim4 0x4000 0400 - 0x4000 07ff tim3 0x4000 0000 - 0x4000 03ff tim2 table 10. stm32f401xb/stm32f401xc register boundary addresses (continued) bus boundary address peripheral docid024738 rev 6 54/135 stm32f401xb stm32f401xc electrical characteristics 113 6 electrical characteristics 6.1 parameter conditions unless otherwise specified, all voltages are referenced to v ss . 6.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean 3 ). 6.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = 3.3 v (for the 1.7 v v dd 3.6 v voltage range). they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean 2 ) . 6.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 16 . figure 16. pin loading conditions - 3 6 # p & - # 5 p i n electrical characteristics stm32f401xb stm32f401xc 55/135 docid024738 rev 6 6.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 17 . figure 17. input voltage measurement - 3 6 - # 5 p i n 6 ) . docid024738 rev 6 56/135 stm32f401xb stm32f401xc electrical characteristics 113 6.1.6 power supply scheme figure 18. power supply scheme 1. to connect pdr_on pin, refer to section 3.14: power supply supervisor . 2. the 4.7 f ceramic capacitor must be connected to one of the v dd pin. 3. v cap_2 pad is only available on lq fp100 and ufbga100 packages. 4. v dda =v dd and v ssa =v ss . caution: each power supply pair (v dd /v ss , v dda /v ssa ...) must be decoupled with filtering ceramic capacitors as shown above. these capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the pcb to ensure good operation of the device. it is not recommended to remove filterin g capacitors to reduce pcb size or cost. this might cause incorrect operation of the device. 0 6 9 % d f n x s f l u f x l w u \ 2 6 & . 5 7 & : d n h x s o r j l f % d f n x s u h j l v w h u v . h u q h o o r j l f & 3 8 g l j l w d o 5 $ 0 $ q d o r j 5 & v 3 / / 3 r z h u v z l w f k 9 % $ 7 * 3 , 2 v 2 8 7 , 1 ? q ) ? ? ) 9 % $ 7 w r 9 9 r o w d j h u h j x o d w r u 9 ' ' $ $ ' & / h y h o v k l i w h u , 2 / r j l f 9 ' ' q ) ? ) ) o d v k p h p r u \ 9 & $ 3 b % < 3 $ 6 6 b 5 ( * 3 ' 5 b 2 1 5 h v h w f r q w u r o o h u 9 ' ' 9 6 6 9 ' ' 9 5 ( ) 9 5 ( ) 9 6 6 $ 9 5 ( ) q ) ? ) 9 & $ 3 b ? ? ) ? ? ) r u electrical characteristics stm32f401xb stm32f401xc 57/135 docid024738 rev 6 6.1.7 current consumption measurement figure 19. current consum ption measurement scheme 6.2 absolute maximum ratings stresses above the absolute maximum ratings listed in table 11: voltage characteristics , table 12: current characteristics , and table 13: thermal characteristics may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. device mission profile (application conditions) is compliant with jedec jesd47 qualificat ion standard. extended mission profiles are available on demand. d l 9 % $ 7 9 ' ' 9 ' ' $ , ' ' b 9 % $ 7 , ' ' table 11. voltage characteristics symbol ratings min max unit v dd ?v ss external main supply voltage (including v dda , v dd and v bat ) (1) 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. ?0.3 4.0 v v in input voltage on ft pins (2) 2. v in maximum value must always be respected. refer to table 12 for the values of the maximum allowed injected current. v ss ?0.3 v dd +4.0 input voltage on any other pin v ss ?0.3 4.0 input voltage for boot0 v ss 9.0 | v ddx | variations between different v dd power pins - 50 mv |v ssx ? v ss | variations between all the different ground pins including v ref- -50 v esd(hbm) electrostatic discharge voltage (human body model) see section 6.3.14: absolute maximum ratings (electrical sensitivity) docid024738 rev 6 58/135 stm32f401xb stm32f401xc electrical characteristics 113 table 12. current characteristics symbol ratings max. unit i vdd total current into sum of all v dd_x power lines (source) (1) 160 ma i vss total current out of sum of all v ss_x ground lines (sink) (1) -160 i vdd maximum current into each v dd_x power line (source) (1) 100 i vss maximum current out of each v ss_x ground line (sink) (1) -100 i io output current sunk by any i/o and control pin 25 output current sourced by any i/o and control pin -25 i io total output current sunk by sum of all i/o and control pins (2) 120 total output current sourced by sum of all i/os and control pins (2) -120 i inj(pin) (3) injected current on ft pins (4) ?5/+0 injected current on nrst and b pins (4) i inj(pin) total injected current (sum of all i/o and control pins) (5) 25 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. 2. this current consumption must be correc tly distributed over all i/os and control pi ns. the total output current must not be sunk/sourced between two consecutive power supply pins referring to high pi n count lqfp packages. 3. negative injection disturbs the analog performance of the device. see note in section 6.3.20: 12-bit adc characteristics . 4. positive injection is not possible on these i/os and does not occur for input voltages lower than the specified maximum value. 5. when several inputs are submitted to a current injection, the maximum i inj(pin) is the absolute sum of the positive and negative injected currents (instantaneous values). table 13. thermal characteristics symbol ratings value unit t stg storage temperature range ?65 to +150 c t j maximum junction temperature 125 t lead maximum lead temperature during soldering (wlcsp49, lqfp64/100, ufqfpn48, ufbga100) see note (1) 1. compliant with jedec std j-std-020d (for small body, sn-pb or pb assembly), the st ecopack ? 7191395 specification, and the european directive on restrictions on hazardous substances (rohs directive 2011/65/eu, july 2011). electrical characteristics stm32f401xb stm32f401xc 59/135 docid024738 rev 6 6.3 operating conditions 6.3.1 general operating conditions table 14. general operating conditions symbol parameter conditions min typ max unit f hclk internal ahb clock frequency power scale3: regulator on, vos[1:0] bits in pwr_cr register = 0x01 0-60 mhz power scale2: regulator on, vos[1:0] bits in pwr_cr register = 0x10 0 - 84 f pclk1 internal apb1 clock frequency 0 - 42 f pclk2 internal apb2 clock frequency 0 - 84 v dd standard operating voltage 1.7 (1) -3.6 v v dda (2)(3) analog operating voltage (adc limited to 1.2 m samples) must be the same potential as v dd (4) 1.7 (1) -2.4 analog operating voltage (adc limited to 2.4 m samples) 2.4 - 3.6 v bat backup operating voltage 1.65 - 3.6 v 12 regulator on: 1.2 v internal voltage on v cap_1 /v cap_2 pins vos[1:0] bits in pwr_cr register = 0x01 max frequency 60 mhz 1.08 (5) 1.14 1.20 (5) vos[1:0] bits in pwr_cr register = 0x10 max frequency 84 mhz 1.20 (5) 1.26 1.32 (5) v 12 regulator off: 1.2 v external voltage must be supplied on v cap_1 /v cap_2 pins max. frequency 60 mhz. 1.1 1.14 1.2 max. frequency 84 mhz. 1.2 1.26 1.32 v in input voltage on rst and ft pins (6) 2v v dd 3.6 v ?0.3 - 5.5 v dd 2v ?0.3 - 5.2 input voltage on boot0 pin 0 - 9 p d maximum allowed package power dissipation for suffix 6 and 7 (7) ufqfpn48 - - 625 mw wlcsp49 - - 385 lqfp64 - - 313 lqfp100 - - 465 ufbga100 - - 323 docid024738 rev 6 60/135 stm32f401xb stm32f401xc electrical characteristics 113 t a ambient temperature for 6 suffix version maximum power dissipation ?40 - 85 c low power dissipation (8) ?40 - 105 ambient temperature for 7 suffix version maximum power dissipation ?40 - 105 low power dissipation (8) ?40 - 125 t j junction temperature range 6 suffix version ?40 - 105 7 suffix version ?40 - 125 1. v dd /v dda minimum value of 1.7 v with the use of an external power supply supervisor (refer to section 3.14.2: internal reset off ). 2. when the adc is used, refer to table 66: adc characteristics . 3. if v ref+ pin is present, it must res pect the following condition: v dda -v ref+ < 1.2 v. 4. it is recommended to power v dd and v dda from the same source. a maximum difference of 300 mv between v dd and v dda can be tolerated during power-up and power-down operation. 5. guaranteed by test in production 6. to sustain a voltage higher than vdd+0.3, the inter nal pull-up and pull-down re sistors must be disabled 7. if t a is lower, higher p d values are allowed as long as t j does not exceed t jmax . 8. in low power dissipation state, t a can be extended to this range as long as t j does not exceed t jmax . table 14. general operating conditions (continued) symbol parameter conditions min typ max unit table 15. features depending on the operating power supply range operating power supply range adc operation maximum flash memory access frequency with no wait states (f flashmax ) maximum flash memory access frequency with wait states (1)(2) i/o operation clock output frequency on i/o pins (3) possible flash memory operations v dd =1.7 to 2.1 v (4) conversion time up to 1.2 msps 20 mhz (5) 84 mhz with 4 wait states ? no i/o compensation up to 30 mhz 8-bit erase and program operations only v dd = 2.1 to 2.4 v conversion time up to 1.2 msps 22 mhz 84 mhz with 3 wait states ? no i/o compensation up to 30 mhz 16-bit erase and program operations v dd = 2.4 to 2.7 v conversion time up to 2.4 msps 24 mhz 84 mhz with 3 wait states ? i/o compensation works up to 48 mhz 16-bit erase and program operations v dd = 2.7 to 3.6 v (6) conversion time up to 2.4 msps 30 mhz 84 mhz with 2 wait states ? i/o compensation works ?up to 84 mhz when v dd = 3.0 to 3.6 v ?up to 48 mhz when v dd = 2.7 to 3.0 v 32-bit erase and program operations electrical characteristics stm32f401xb stm32f401xc 61/135 docid024738 rev 6 6.3.2 vcap_1/vcap_2 external capacitors stabilization for the main regula tor is achieved by connecting 2 external capacitor c ext to the vcap_1 and vcap_2 pins. for packages supporting only 1 vcap pin, the 2 cext capacitors are replaced by a single capacitor. c ext is specified in table 16 . figure 20. external capacitor c ext 1. legend: esr is the equivalent series resistance. 6.3.3 operating conditions at pow er-up/power-down (regulator on) subject to general operating conditions for t a . table 17. operating conditions at power-up / power-down (regulator on) 1. applicable only when the code is executed from flash memory. when the code is executed from ram, no wait state is required. 2. thanks to the art accelerator and the 128-bit flash memory, the number of wait states given here does not impact the execution speed from flash memory since the art accelerator allows to achieve a performance equivalent to 0 wait state program execution. 3. refer to table 56: i/o ac characteristics for frequencies vs. external load. 4. v dd /v dda minimum value of 1.7 v, with the use of an external power supply supervisor (refer to section 3.14.2: internal reset off ). 5. prefetch is not available. refer to an3430 application note for details on how to adjust performance and power. 6. the voltage range for the usb full speed embedded phy can drop do wn to 2.7 v. however the elec trical characteristics of d- and d+ pins will be degraded between 2.7 and 3 v. table 16. vcap_1/vcap _2 operating conditions (1) 1. when bypassing the voltage regulator, the two 2.2 f v cap capacitors are not required and should be replaced by two 100 nf decoupling capacitors. symbol paramete r conditions cext capacitance of external capacitor with available vcap_1 and vcap_2 pins 2.2 f esr esr of external capacitor with available vcap_1 and vcap_2 pins < 2 0 6 9 ( 6 5 5 / h d n & symbol parameter min max unit t vdd v dd rise time rate 20 s/v v dd fall time rate 20 docid024738 rev 6 62/135 stm32f401xb stm32f401xc electrical characteristics 113 6.3.4 operating conditi ons at power-up / powe r-down (regulator off) subject to general operating conditions for t a . note: this feature is only available for ufbga100 package. 6.3.5 embedded reset and power control block characteristics the parameters given in table 19 are derived from tests performed under ambient temperature and v dd supply voltage @ 3.3v. table 18. operating conditions at power-up / power-down (regulator off) (1) 1. to reset the internal logic at power-down, a reset must be applied on pin pa0 when v dd reach below 1.08 v. symbol parameter conditions min max unit t vdd v dd rise time rate power-up 20 s/v v dd fall time rate power-down 20 t vcap v cap_1 and v cap_2 rise time rate power-up 20 v cap_1 and v cap_2 fall time rate power-down 20 table 19. embedded reset and power control block characteristics symbol parameter conditions min typ max unit v pvd programmable voltage detector level selection pls[2:0]=000 (rising edge) 2.09 2.14 2.19 v pls[2:0]=000 (falling edge) 1.98 2.04 2.08 pls[2:0]=001 (rising edge) 2.23 2.30 2.37 pls[2:0]=001 (falling edge) 2.13 2.19 2.25 pls[2:0]=010 (rising edge) 2.39 2.45 2.51 pls[2:0]=010 (falling edge) 2.29 2.35 2.39 pls[2:0]=011 (rising edge) 2.54 2.60 2.65 pls[2:0]=011 (falling edge) 2.44 2.51 2.56 pls[2:0]=100 (rising edge) 2.70 2.76 2.82 pls[2:0]=100 (falling edge) 2.59 2.66 2.71 pls[2:0]=101 (rising edge) 2.86 2.93 2.99 pls[2:0]=101 (falling edge) 2.65 2.84 2.92 pls[2:0]=110 (rising edge) 2.96 3.03 3.10 pls[2:0]=110 (falling edge) 2.85 2.93 2.99 pls[2:0]=111 (rising edge) 3.07 3.14 3.21 pls[2:0]=111 (falling edge) 2.95 3.03 3.09 v pvdhyst (2) pvd hysteresis - 100 - mv v por/pdr power-on/power-down reset threshold falling edge 1.60 (1) 1.68 1.76 v rising edge 1.64 1.72 1.80 electrical characteristics stm32f401xb stm32f401xc 63/135 docid024738 rev 6 6.3.6 supply current characteristics the current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, i/o pi n loading, device software configuration, operating frequencies, i/o pin switching rate, program location in memory and executed binary code. the current consumption is measured as described in figure 19: current consumption measurement scheme . all the run-mode current consumption measurements given in this section are performed with a reduced code that gives a consum ption equivalent to coremark code. v pdrhyst (2) pdr hysteresis - 40 - mv v bor1 brownout level 1 threshold falling edge 2.13 2.19 2.24 v rising edge 2.23 2.29 2.33 v bor2 brownout level 2 threshold falling edge 2.44 2.50 2.56 rising edge 2.53 2.59 2.63 v bor3 brownout level 3 threshold falling edge 2.75 2.83 2.88 rising edge 2.85 2.92 2.97 v borhyst (2) bor hysteresis - 100 - mv t rsttempo (2)(3) por reset timing 0.5 1.5 3.0 ms i rush (2) inrush current on voltage regulator power- on (por or wakeup from standby) - 160 200 ma e rush (2) inrush energy on voltage regulator power- on (por or wakeup from standby) v dd = 1.7 v, t a = 105 c, i rush = 171 ma for 31 s --5.4c 1. the product behavior is guaranteed by design down to the minimum v por/pdr value. 2. guaranteed by design. 3. the reset timing is measured from the power-on (por reset or wakeup from v bat ) to the instant when first instruction is fetched by the user application code. table 19. embedded reset and power control block characteristics (continued) symbol parameter conditions min typ max unit docid024738 rev 6 64/135 stm32f401xb stm32f401xc electrical characteristics 113 typical and maximum current consumption the mcu is placed under the following conditions: ? all i/o pins are in input mode with a static value at vdd or vss (no load). ? all peripherals are disabled except if it is explicitly mentioned. ? the flash memory access time is adjusted to both f hclk frequency and vdd ranges (refer to table 15: features depending on the operating power supply range ). ? the voltage scaling is adjusted to f hclk frequency as follows: ? scale 3 for f hclk 60 mhz ? scale 2 for 60 mhz < f hclk 84 mhz ? the system clock is hclk, f pclk1 = f hclk /2, and f pclk2 = f hclk . ? external clock is 4 mhz and pll is on when f hclk is higher than 25 mhz. ? the maximum values are obtained for v dd = 3.6 v and a maximum ambient temperature (t a ), and the typical values for t a = 25 c and v dd = 3.3 v unless otherwise specified. table 20. typical and maximum current consum ption, code with data processing (art accelerator disabled) running from sram - v dd =1.8v symbol parameter conditions f hclk (mhz) typ max (1) unit t a = 25 c t a =85 c t a =105 c i dd supply current in run mode external clock, all peripherals enabled (2)(3) 84 20.0 21 22 23 (4) ma 60 14.5 15 16 17 40 10.4 11 12 13 20 5.5 6 7 8 external clock, all peripherals disabled (3) 84 10.9 11 13 14 (4) 60 8.0 9 10 11 40 5.8 6 7 8 20 3.2 4 5 6 1. guaranteed by characterization, unless otherwise specified. 2. when analog peripheral blocks such as adc, hse, lse, hs i, or lsi are on, an additional power consumption has to be considered. 3. when the adc is on (adon bit set in the adc_cr2 regist er), add an additional power consumption of 1.6 ma for the analog part. 4. guaranteed by test in production. electrical characteristics stm32f401xb stm32f401xc 65/135 docid024738 rev 6 table 21. typical and maximum current consum ption, code with data processing (art accelerator disabled) running from sram symbol parameter conditions f hclk (mhz) typ max (1) unit t a = 25 c t a =85 c t a =105 c i dd supply current in run mode external clock, all peripherals enabled (2)(3) 84 20.2 21 22 23 ma 60 14.7 15 16 18 40 10.7 11 12 13 20 5.7 6 7 8 external clock, all peripherals disabled (3) 84 11.2 12 13 14 60 8.2 9 10 11 40 6.1 7 8 9 20 3.4 4 5 6 1. guaranteed by characterization, unless otherwise specified. 2. when analog peripheral blocks such as adc, hse, lse, hs i, or lsi are on, an additional power consumption has to be considered. 3. when the adc is on (adon bit set in the adc_cr2 regist er), add an additional power consumption of 1.6 ma for the analog part. table 22. typical and maximum current consumption in run mode, code with data processing (art accelerator enabled except prefetch) running from flash memory- v dd = 1.8 v symbol parameter conditions f hclk (mhz) typ max (1) unit t a = 25 c t a = 85 c t a = 105 c i dd supply current in run mode external clock, all peripherals enabled (2) (3) 84 22.2 23 24 25 ma 60 14.5 15 16 17 40 10.7 11 12 13 30 8.6 9 10 11 20 7.0 8 9 10 external clock, all peripherals disabled (3) 84 11.5 12 13 14 60 7.7 8 9 10 40 5.6 6 7 8 30 4.5 5 6 7 20 3.8 5 6 7 1. guaranteed by characterization, unless otherwise specified. 2. add an additional power consumption of 1.6 ma per adc for the analog part. in applications, this consumption occurs only while the adc is on (adon bit is set in the adc_cr2 register). 3. when the adc is on (adon bit set in the adc_cr2), add an additional power consumption of 1.6ma per adc for the analog part. docid024738 rev 6 66/135 stm32f401xb stm32f401xc electrical characteristics 113 . table 23. typical and maximum current consumption in run mode, code with data processing (art accelerator enabled except prefetch) running from flash memory - v dd = 3.3 v symbol parameter conditions f hclk (mhz) typ max (1) unit t a = 25 c t a = 85 c t a = 105 c i dd supply current in run mode external clock, all peripherals enabled (2) (3) 84 22.5 23 24 25 ma 60 14.8 16 17 18 40 11.0 12 13 14 30 8.9 10 11 12 20 7.3 8 9 10 external clock, all peripherals disabled (3) 84 11.8 13 14 15 60 7.9 9 10 11 40 5.8 7 8 9 30 4.8 6 7 8 20 4.0 5 6 7 1. guaranteed by characterization, unless otherwise specified. 2. add an additional power consumption of 1.6 ma per adc for the analog part. in applications, this consumption occurs only while the adc is on (adon bit is set in the adc_cr2 register). 3. when the adc is on (adon bit set in the adc_cr2), add an additional power consumption of 1.6ma per adc for the analog part. table 24. typical and maximum current consumption in run mode, code with data processing (art accelerator disabled) running from flash memory symbol parameter conditions f hclk (mhz) typ max (1) unit t a = 25 c t a = 85 c t a = 105 c i dd supply current in run mode external clock, all peripherals enabled (2) (3) 84 30.6 32 34 35 ma 60 21.4 22 24 25 40 15.6 16 17 18 30 12.7 13 14 15 20 10.0 11 12 13 external clock, all peripherals disabled (3) 84 19.9 21 23 25 60 14.6 15 16 17 40 10.4 11 12 13 30 8.6 9 10 11 20 6.7 7 8 9 1. guaranteed by characterization, unless otherwise specified. 2. add an additional power consumption of 1.6 ma per adc for the analog part. in applications, this consumption occurs only while the adc is on (adon bit is set in the adc_cr2 register). 3. when the adc is on (adon bit set in the adc_cr2), add an additional power consumption of 1.6ma per adc for the analog part. electrical characteristics stm32f401xb stm32f401xc 67/135 docid024738 rev 6 table 25. typical and maximum current consumption in run mode, code with data processing (art accelerator enabled with prefetch) running from flash memory symbol parameter conditions f hclk (mhz) typ max (1) unit t a = 25 c t a = 85 c t a = 105 c i dd supply current in run mode external clock, all peripherals enabled (2) (3) 84 31.8 33 35 36 ma 60 21.8 22 23 24 40 16.0 17 18 19 30 12.9 14 15 16 20 10.4 11 12 13 external clock, all peripherals disabled (3) 84 21.2 22 23 24 60 15.0 16 17 18 40 10.9 12 13 14 30 8.8 10 11 12 20 7.1 8 9 10 1. guaranteed by characterization, unless otherwise specified. 2. add an additional power consumption of 1.6 ma per adc for the analog part. in applications, this consumption occurs only while the adc is on (adon bit is set in the adc_cr2 register). 3. when the adc is on (adon bit set in the adc_cr2), add an additional power consumption of 1.6ma per adc for the analog part. table 26. typical and maximum current consumption in sleep mode symbol parameter conditions f hclk (mhz) typ max (1) unit t a = 25 c t a = 85 c t a = 105 c i dd supply current in sleep mode external clock, all peripherals enabled (2) (3) 84 16.2 17 18 19 ma 60 10.7 11 12 13 40 8.3 9 10 11 30 6.8 7 8 9 20 5.9 6 7 8 external clock, all peripherals disabled (3)(4) 84 5.2 6 7 8 60 3.6 4 5 6 40 2.9 3 4 5 30 2.6 3 4 5 20 2.6 3 4 5 1. guaranteed by characterization, unless otherwise specified. 2. add an additional power consumption of 1.6 ma per adc for the analog part. in applications, this consumption occurs only while the adc is on (adon bit is set in the adc_cr2 register). 3. when the adc is on (adon bit set in the adc_cr2 regist er), add an additional power consumption of 1.6 ma for the analog part. 4. same current consumption for f hclk at 30 mhz and 20 mhz due to vco running slower at 30 mhz. docid024738 rev 6 68/135 stm32f401xb stm32f401xc electrical characteristics 113 table 27. typical and maximum current consumptions in stop mode - v dd =1.8 v symbol parameter conditions typ max (1) unit t a = 25 c t a = 25 c t a = 85 c t a = 105 c i dd_stop main regulator usage flash in stop mode, all oscillators off, no independent watchdog 109 135 440 650 a low power regulator usage 41 65 310 530 (2) main regulator usage flash in deep power down mode, all oscillators off, no independent watchdog 72 95 345 530 low power regulator usage 12 36 260 510 (2) low power low voltage regulator usage 10 27 230 460 1. guaranteed by characterization. 2. guaranteed by test in production. table 28. typical and maximum current consumption in stop mode - v dd =3.3 v symbol parameter conditions typ max (1) unit t a = 25 c t a = 25 c t a = 85 c t a = 105 c i dd_stop main regulator usage flash in stop mode, all oscillators off, no independent watchdog 111 140 450 670 a low power regulator usage 42 65 330 560 main regulator usage flash in deep power down mode, all oscillators off, no independent watchdog 73 100 360 560 low power regulator usage 12 36 270 520 low power low voltage regulator usage 10 28 230 470 1. guaranteed by characterization. table 29. typical and maximum current consumption in standby mode - v dd =1.8 v symbol parameter conditions typ (1) max (2) unit t a = 25 c t a = 25 c t a = 85 c t a = 105 c i dd_stby supply current in standby mode low-speed oscillator (lse) and rtc on 2.4 4.0 12.0 24.0 a rtc and lse off 1.8 3.0 (3) 11.0 23.0 (3) 1. when the pdr is off (internal reset is off), t he typical current consumption is reduced by 1.2 a. 2. guaranteed by characterization, unless otherwise specified. 3. guaranteed by test in production. electrical characteristics stm32f401xb stm32f401xc 69/135 docid024738 rev 6 figure 21. typical v bat current consumption (lse and rtc on) table 30. typical and maximum current consumption in standby mode - v dd =3.3 v symbol parameter conditions typ (1) max (2) unit t a = 25 c t a = 25 c t a = 85 c t a = 105 c i dd_stby supply current in standby mode low-speed oscillator (lse) and rtc on 2.8 5.0 14.0 28.0 a rtc and lse off 2.1 4.0 (3) 13.0 27.0 (3) 1. when the pdr is off (internal reset is off), t he typical current consumption is reduced by 1.2 a. 2. guaranteed by characterization, unless otherwise specified. 3. guaranteed by test in production. table 31. typical and maximum current consumptions in v bat mode symbol parameter conditions (1) typ max (2) unit t a = 25 c t a = 85 c t a = 105 c v bat = 1.7 v v bat = 2.4 v v bat = 3.3 v v bat = 3.6 v i dd_vbat backup domain supply current low-speed oscillator (lse) and rtc on 0.66 0.76 0.97 3.0 5.0 a rtc and lse off 0.1 0.1 0.1 2.0 4.0 1. crystal used: abracon abs07-120-32.768 khz-t with a c l of 6 pf for typical values. 2. guaranteed by characterization. - 3 6 ? # ? # ? # ? # ? # ) $ $ ? 6 " ! 4 ? ! 4 e m p e r a t u r e 6 6 6 6 6 6 6 6 6 docid024738 rev 6 70/135 stm32f401xb stm32f401xc electrical characteristics 113 i/o system current consumption the current consumption of the i/o system has two components: static and dynamic. i/o static current consumption all the i/os used as inputs with pull-up ge nerate current consumpt ion when the pin is externally held low. the value of this current consumption can be simply computed by using the pull-up/pull-down resi stors values given in table 54: i/o static characteristics . for the output pins, any external pull-down or external load must also be considered to estimate the current consumption. additional i/o current consumption is due to i/os configured as inputs if an intermediate voltage level is externally applie d. this current consumption is caused by the input schmitt trigger circuits used to discriminate the input va lue. unless this spec ific configuration is required by the application, this supply curr ent consumption can be avoided by configuring these i/os in analog mode. this is notably the case of adc input pins which should be configured as analog inputs. caution: any floating input pin can also settle to an in termediate voltage level or switch inadvertently, as a result of external electromagnetic nois e. to avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. this can be done either by usin g pull-up/down resistors or by configuring the pins in output mode. i/o dynamic current consumption in addition to the internal peripheral current consumption (see table 33: peripheral current consumption ), the i/os used by an application also contribute to the current consumption. when an i/o pin switches, it uses the current from the mcu supply voltage to supply the i/o pin circuitry and to charge/discharge the capaci tive load (internal or external) connected to the pin: where i sw is the current sunk by a switching i/ o to charge/discharge the capacitive load v dd is the mcu supply voltage f sw is the i/o switching frequency c is the total capacitance seen by the i/o pin: c = c int + c ext the test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. i sw v dd f sw c = electrical characteristics stm32f401xb stm32f401xc 71/135 docid024738 rev 6 table 32. switching output i/o current consumption symbol parameter conditions (1) 1. c s is the pcb board capacitance including the pad pin. c s = 7 pf (estimated value). i/o toggling frequency (f sw ) typ unit iddio i/o switching current v dd = 3.3 v c = c int (2) 2. this test is performed by cutting the lqfp100 package pin (pad removal). 2 mhz 0.05 ma 8 mhz 0.15 25 mhz 0.45 50 mhz 0.85 60 mhz 1.00 84 mhz 1.40 v dd = 3.3 v c ext = 0 pf c = c int + c ext + c s 2 mhz 0.10 8 mhz 0.35 25 mhz 1.05 50 mhz 2.20 60 mhz 2.40 84 mhz 3.55 v dd = 3.3 v c ext =10 pf c = c int + c ext + c s 2 mhz 0.20 8 mhz 0.65 25 mhz 1.85 50 mhz 2.45 60 mhz 4.70 84 mhz 8.80 v dd = 3.3 v c ext = 22 pf c = c int + c ext + c s 2 mhz 0.25 8 mhz 1.00 25 mhz 3.45 50 mhz 7.15 60 mhz 11.55 v dd = 3.3 v c ext = 33 pf c = c int + c ext + c s 2 mhz 0.32 8 mhz 1.27 25 mhz 3.88 50 mhz 12.34 docid024738 rev 6 72/135 stm32f401xb stm32f401xc electrical characteristics 113 on-chip peripheral current consumption the mcu is placed under the following conditions: ? at startup, all i/o pins are in analog input configuration. ? all peripherals are disabled unless otherwise mentioned. ? the art accelerator is on. ? voltage scale 2 mode selected, internal digital voltage v12 = 1.26 v. ? hclk is the system clock at 84 mhz. f pclk1 = f hclk /2, and f pclk2 = f hclk . the given value is calculated by measur ing the difference of current consumption ? with all peripherals clocked off ? with only one peripheral clocked on ? ambient operating temperature is 25 c and v dd =3.3 v. table 33. peripheral current consumption peripheral i dd (typ) unit ahb1 (up to 84mhz) gpioa 1.55 a/mhz gpiob 1.55 gpioc 1.55 gpiod 1.55 gpioe 1.55 gpioh 1.55 crc 0.36 dma1 20.24 dma2 21.07 apb1 (up to 42mhz) tim2 11.19 a/mhz tim3 8.57 tim4 8.33 tim5 11.19 pwr 0.71 usart2 3.33 i2c1/2/3 3.10 spi2 (1) 2.62 spi3 (1) 2.86 i2s2 1.90 i2s3 1.67 wwdg 0.71 ahb2 (up to 84mhz) otg_fs 23.93 a/mhz electrical characteristics stm32f401xb stm32f401xc 73/135 docid024738 rev 6 6.3.7 wakeup time from low-power modes the wakeup times given in table 34 are measured starting from the wakeup event trigger up to the first instruction executed by the cpu: ? for stop or sleep modes: the wakeup event is wfe. ? wkup (pa0) pin is used to wakeup from standby, stop and sleep modes. all timings are derived from tests performed under ambient temperature and v dd =3.3 v. apb2 (up to 84mhz) tim1 5.71 a/mhz tim9 2.86 tim10 1.79 tim11 2.02 adc1 (2) 2.98 spi1 1.19 usart1 3.10 usart6 2.86 sdio 5.95 spi4 1.31 syscfg 0.71 1. i2smod bit set in spi_i2scfgr register, and then the i2se bit set to enable i2s peripheral. 2. when the adc is on (adon bit set in the adc_cr2 register), add an additional power consumption of 1.6 ma for the analog part. table 33. peripheral current consumption (continued) peripheral i dd (typ) unit table 34. low-power mode wakeup timings (1) symbol parameter min (1) typ (1) max (1) unit t wusleep (2) wakeup from sleep mode - 4 6 cpu clock cycle t wustop (2) wakeup from stop mode, usage of main regulator - 13.5 14.5 s wakeup from stop mode, usage of main regulator, flash memory in deep power down mode -105111 wakeup from stop mode, regulator in low power mode - 21 33 wakeup from stop mode, regulator in low power mode, flash memory in deep power down mode - 113 130 t wustdby (2)(3) wakeup from standby mode - 314 407 s 1. guaranteed by characterization. 2. the wakeup times are measured from the wakeup event to the point in which the application c ode reads the first instruction. 3. t wustdby maximum value is given at ?40 c. docid024738 rev 6 74/135 stm32f401xb stm32f401xc electrical characteristics 113 6.3.8 external clock source characteristics high-speed external user clock generated from an external source in bypass mode the hse oscillator is switched off and the input pin is a standard i/o. the external clock signal has to respect the table 54 . however, the recommended clock input waveform is shown in figure 22 . the characteristics given in table 35 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in table 14 . low-speed external user clock generated from an external source in bypass mode the lse oscillato r is switched off and the inpu t pin is a standard i/o. the external clock signal has to respect the table 54 . however, the recommended clock input waveform is shown in figure 23 . the characteristics given in table 36 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in table 14 . table 35. high-speed external user clock characteristics symbol parameter condi tions min typ max unit f hse_ext external user clock source frequency (1) 1-50mhz v hseh osc_in input pin high level voltage 0.7v dd -v dd v v hsel osc_in input pin low level voltage v ss -0.3v dd t w(hse) t w(hse) osc_in high or low time (1) 1. guaranteed by design. 5-- ns t r(hse) t f(hse) osc_in rise or fall time (1) --10 c in(hse) osc_in input capacitance (1) -5-pf ducy (hse) duty cycle 45 - 55 % i l osc_in input leakage current v ss v in v dd --1a electrical characteristics stm32f401xb stm32f401xc 75/135 docid024738 rev 6 figure 22. high-speed external clock source ac timing diagram table 36. low-speed external user clock characteristics symbol parameter conditions min typ max unit f lse_ext user external clock source frequency (1) - 32.768 1000 khz v lseh osc32_in input pin high level voltage 0.7v dd -v dd v v lsel osc32_in input pin low level voltage v ss -0.3v dd t w(lse) t f(lse) osc32_in high or low time (1) 450 - - ns t r(lse) t f(lse) osc32_in rise or fall time (1) --50 c in(lse) osc32_in input capacitance (1) -5-pf ducy (lse) duty cycle 30 - 70 % i l osc32_in input leakage current v ss v in v dd --1a 1. guaranteed by design. a i / 3 # ? ) . % x t e r n a l 3 4 - & c l o c k s o u r c e 6 ( 3 % ( t f ( 3 % t 7 ( 3 % ) , 4 ( 3 % t t r ( 3 % t 7 ( 3 % f ( 3 % ? e x t 6 ( 3 % , docid024738 rev 6 76/135 stm32f401xb stm32f401xc electrical characteristics 113 figure 23. low-speed external clock source ac timing diagram high-speed external clock generated from a crystal/ceramic resonator the high-speed external (hse) clock can be supplied with a 4 to 26 mhz crystal/ceramic resonator oscillator. all th e information given in this paragraph are based on characterization results obtained with typical external components specified in table 37 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion an d startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequenc y, package, accuracy). for c l1 and c l2 , it is recommended to use high-quality external ceramic capacitors in the 5 pf to 25 pf range (typ.), designed for high- frequency applications, and selected to match the requirements of the crystal or resonator (see figure 24 ). c l1 and c l2 are usually the same size. the crystal manufacturer typically specifies a load capacitance which is the table 37. hse 4-26 mhz oscillator characteristics (1) 1. guaranteed by design. symbol parameter condi tions min typ max unit f osc_in oscillator frequency 4 - 26 mhz r f feedback resistor - 200 - k i dd hse current consumption v dd =3.3 v, esr= 30 , c l =5 pf @25 mhz -450- a v dd =3.3 v, esr= 30 , c l =10 pf @25 mhz -530- g m_crit_max maximum critical crystal g m startup - - 1 ma/v t su(hse) (2) 2. t su(hse) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 mhz oscillation is reached. this value is measured for a standard crystal res onator and it can vary significantly with the crystal manufacturer startup time v dd is stabilized - 2 - ms d l 2 6 & b , 1 ( [ w h u q d o 6 7 0 ) f o r f n v r x u f h 9 / 6 ( + w i / 6 ( w : / 6 ( , / 7 / 6 ( w w u / 6 ( w : / 6 ( i / 6 ( b h [ w 9 / 6 ( / electrical characteristics stm32f401xb stm32f401xc 77/135 docid024738 rev 6 series combination of c l1 and c l2 . pcb and mcu pin capacitance must be included (10 pf can be used as a rough estimate of the comb ined pin and board capacitance) when sizing c l1 and c l2 . note: for information on selecting the crystal, refer to the application note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com. figure 24. typical application with an 8 mhz crystal 1. r ext value depends on the cr ystal characteristics. low-speed external clock generated from a crystal/ceramic resonator the low-speed external (lse) clock can be supplied with a 32.768 khz crystal/ceramic resonator oscillator. all th e information given in this paragraph are based on characterization results obtained with typical external components specified in table 38 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion an d startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequenc y, package, accuracy). note: for information on selecting the crystal, refer to the application note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com. table 38. lse oscillator characteristics (f lse = 32.768 khz) (1) 1. guaranteed by design. symbol parameter condi tions min typ max unit r f feedback resistor - 18.4 - m i dd lse current consumption - - 1 a g m _crit_max maximum critical crystal g m startup - - 0.56 a/v t su(lse) (2) 2. t su(lse) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 khz oscillation is reached. this value is guaranteed by characterizati on. it is measured for a standard crystal resonator and it can vary signi ficantly with the crystal manufacturer. startup time v dd is stabilized - 2 - s d l 2 6 & b 2 8 7 2 6 & b , 1 i + 6 ( & / 5 ) 6 7 0 ) 0 + ] u h v r q d w r u 5 h v r q d w r u z l w k l q w h j u d w h g f d s d f l w r u v % l d v f r q w u r o o h g j d l q 5 ( ; 7 & / docid024738 rev 6 78/135 stm32f401xb stm32f401xc electrical characteristics 113 figure 25. typical applicati on with a 32.768 khz crystal 6.3.9 internal clock source characteristics the parameters given in table 39 and table 40 are derived from tests performed under ambient temperature and v dd supply voltage condit ions summarized in table 14 . high-speed internal (hsi) rc oscillator d l 2 6 & b 2 8 7 2 6 & b , 1 i / 6 ( & / 5 ) 6 7 0 ) n + ] u h v r q d w r u 5 h v r q d w r u z l w k l q w h j u d w h g f d s d f l w r u v % l d v f r q w u r o o h g j d l q & / table 39. hsi oscillator characteristics (1) 1. v dd = 3.3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter conditions min typ max unit f hsi frequency - - 16 - mhz acc hsi hsi user trimming step (2) 2. guaranteed by design. ---1% accuracy of the hsi oscillator t a = ?40 to 105 c (3) 3. guaranteed by characterization. ?8 - 4.5 % t a = ?10 to 85 c (3) ?4 - 4 % t a = 25 c (4) 4. factory calibrated, parts not soldered. ?1 - 1 % t su(hsi) (2) hsi oscillator startup time - - 2.2 4 s i dd(hsi) (2) hsi oscillator power consumption - - 60 80 a electrical characteristics stm32f401xb stm32f401xc 79/135 docid024738 rev 6 figure 26. acc hsi versus temperature 1. guaranteed by characterization. low-speed internal (lsi) rc oscillator table 40. lsi oscillator characteristics (1) 1. v dd = 3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter min typ max unit f lsi (2) 2. guaranteed by characterization. frequency 17 32 47 khz t su(lsi) (3) 3. guaranteed by design. lsi oscillator startup time - 15 40 s i dd(lsi) (3) lsi oscillator power consumption - 0.4 0.6 a 0 6 y 9 $ & & + 6 , 7 $ ? & 0 l q 0 d [ 7 \ s l f d o docid024738 rev 6 80/135 stm32f401xb stm32f401xc electrical characteristics 113 figure 27. acc lsi versus temperature 6.3.10 pll characteristics the parameters given in table 41 and table 42 are derived from tests performed under temperature and v dd supply voltage conditions summarized in table 14 . - 3 6 . o r m a l i z e d d e v i a t i o n 4 e m p e r a t u r e ? # m a x a v g m i n table 41. main pll characteristics symbol parameter conditions min typ max unit f pll_in pll input clock (1) 0.95 (2) 12.10mhz f pll_out pll multiplier output clock 24 - 84 mhz f pll48_out 48 mhz pll multiplier output clock -48 75mhz f vco_out pll vco output 192 - 432 mhz t lock pll lock time vco freq = 192 mhz 75 - 200 s vco freq = 432 mhz 100 - 300 jitter (3) cycle-to-cycle jitter system clock 84 mhz rms - 25 - ps peak to peak - 150 - period jitter rms - 15 - peak to peak - 200 - electrical characteristics stm32f401xb stm32f401xc 81/135 docid024738 rev 6 i dd(pll) (4) pll power consumption on vdd vco freq = 192 mhz vco freq = 432 mhz 0.15 0.45 - 0.40 0.75 ma i dda(pll) (4) pll power consumption on vdda vco freq = 192 mhz vco freq = 432 mhz 0.30 0.55 - 0.40 0.85 1. take care of using the appropriate division factor m to obtai n the specified pll input clock values. the m factor is shared between pll and plli2s. 2. guaranteed by design. 3. the use of 2 plls in parallel could degraded the jitter up to +30%. 4. guaranteed by characterization. table 41. main pll characteristics (continued) symbol parameter conditions min typ max unit table 42. plli2s (audio pll) characteristics symbol parameter conditions min typ max unit f plli2s_in plli2s input clock (1) 0.95 (2) 12.10 mhz f plli2s_out plli2s multiplier output clock - - 216 f vco_out plli2s vco output 192 - 432 t lock plli2s lock time vco freq = 192 mhz 75 - 200 s vco freq = 432 mhz 100 - 300 jitter (3) master i2s clock jitter cycle to cycle at 12.288 mhz on 48 khz period, n=432, r=5 rms - 90 - peak to peak - 280 - ps average frequency of 12.288 mhz n = 432, r = 5 on 1000 samples -90 - ws i2s clock jitter cycle to cycle at 48 khz on 1000 samples - 400 - i dd(plli2s) (4) plli2s power consumption on v dd vco freq = 192 mhz vco freq = 432 mhz 0.15 0.45 - 0.40 0.75 ma i dda(plli2s) (4) plli2s power consumption on v dda vco freq = 192 mhz vco freq = 432 mhz 0.30 0.55 - 0.40 0.85 1. take care of using the appropriate division factor m to have the specified pll input clock values. 2. guaranteed by design. 3. value given with main pll running. 4. guaranteed by characterization. docid024738 rev 6 82/135 stm32f401xb stm32f401xc electrical characteristics 113 6.3.11 pll spread spectrum clo ck generation (sscg) characteristics the spread spectrum clock generation (sscg) feature allows to reduce electromagnetic interferences (see table 49: emi characteristics for wlcsp49 ). it is available only on the main pll. equation 1 the frequency modulation period (modeper) is given by the equation below: f pll_in and f mod must be expressed in hz. as an example: if f pll_in = 1 mhz, and f mod = 1 khz, the modulation dep th (modeper) is given by equation 1: equation 2 equation 2 allows to calculate the increment step (incstep): f vco_out must be expressed in mhz. with a modulation depth (md) = 2 % (4 % peak to peak), and plln = 240 (in mhz): an amplitude quantization error may be generat ed because the linear modulation profile is obtained by taking the quantized values (roun ded to the nearest integer) of modper and incstep. as a result, the achieved modulation depth is quantized. the percentage quantized modulation depth is given by the following formula: as a result: table 43. sscg parameters constraint symbol parameter min typ max (1) unit f mod modulation frequency - - 10 khz md peak modulation depth 0.25 - 2 % modeper * incstep - - 2 15 -1 - 1. guaranteed by design. modeper round f pll_in 4f mod () ? [] = modeper round 10 6 410 3 () ? [] 250 == incstep round 2 15 1 ? () md plln () 100 5 modeper () ? [] = incstep round 2 15 1 ? () 2240 () 100 5 250 () ? [] 126md(quantitazed)% == md quantized % modeper incstep 100 5 () 2 15 1 ? () plln () ? = md quantized % 250 126 100 5 () 2 15 1 ? () 240 () ? 2.002%(peak) == electrical characteristics stm32f401xb stm32f401xc 83/135 docid024738 rev 6 figure 28 and figure 29 show the main pll output clock waveforms in center spread and down spread modes, where: f0 is f pll_out nominal. t mode is the modulation period. md is the modulation depth. figure 28. pll output clock waveforms in center spread mode figure 29. pll output clock waveforms in down spread mode 6.3.12 memory characteristics flash memory the characteristics are given at t a = ? 40 to 105 c unless otherwise specified. the devices are shipped to customers with the flash memory erased. & r e q u e n c y 0 , , ? / 5 4 4 i m e & t m o d e x t m o d e m d a i m d ) u h t x h q f \ 3 / / b 2 8 7 7 l p h ) w p r g h [ w p r g h [ p g d l e table 44. flash memory characteristics symbol parameter conditions min typ max unit i dd supply current write / erase 8-bit mode, v dd = 1.7 v - 5 - ma write / erase 16-bit mode, v dd = 2.1 v - 8 - write / erase 32-bit mode, v dd = 3.3 v - 12 - docid024738 rev 6 84/135 stm32f401xb stm32f401xc electrical characteristics 113 table 45. flash memory programming symbol parameter conditions min (1) typ max (1) 1. guaranteed by characterization. unit t prog word programming time program/erase parallelism (psize) = x 8/16/32 -16100 (2) 2. the maximum programming time is m easured after 100k erase operations. s t erase16kb sector (16 kb) erase time program/erase parallelism (psize) = x 8 - 400 800 ms program/erase parallelism (psize) = x 16 - 300 600 program/erase parallelism (psize) = x 32 - 250 500 t erase64kb sector (64 kb) erase time program/erase parallelism (psize) = x 8 - 1200 2400 ms program/erase parallelism (psize) = x 16 - 700 1400 program/erase parallelism (psize) = x 32 - 550 1100 t erase128kb sector (128 kb) erase time program/erase parallelism (psize) = x 8 -24 s program/erase parallelism (psize) = x 16 -1.32.6 program/erase parallelism (psize) = x 32 -12 t me mass erase time program/erase parallelism (psize) = x 8 -48 s program/erase parallelism (psize) = x 16 - 2.75 5.5 program/erase parallelism (psize) = x 32 -24 v prog programming voltage 32-bit program operation 2.7 - 3.6 v 16-bit program operation 2.1 - 3.6 v 8-bit program operation 1.7 - 3.6 v table 46. flash memory programming with v pp voltage symbol parameter conditions min (1) typ max (1) unit t prog double word programming t a = 0 to +40 c v dd = 3.3 v v pp = 8.5 v - 16 100 (2) s t erase16kb sector (16 kb) erase time - 230 - ms t erase64kb sector (64 kb) erase time - 490 - t erase128kb sector (128 kb) erase time - 875 - t me mass erase time - 1.750 - s electrical characteristics stm32f401xb stm32f401xc 85/135 docid024738 rev 6 table 47. flash memory endurance and data retention 6.3.13 emc characteristics susceptibility tests are perf ormed on a sample basis duri ng device characterization. functional ems (electromagnetic susceptibility) while a simple application is executed on t he device (toggling 2 leds through i/o ports). the device is stressed by two electromagnetic events until a failure o ccurs. the failure is indicated by the leds: ? electrostatic discharge (esd) (positive and negative) is applied to all device pins until a functional disturbance occurs. this test is compliant with the iec 61000-4-2 standard. ? ftb : a burst of fast transient voltage (p ositive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a functional disturbance occurs. this test is compliant with the iec 61000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in table 48 . they are based on the ems levels and classes defined in application note an1709. v prog programming voltage 2.7 - 3.6 v v pp v pp voltage range 7 - 9 v i pp minimum current sunk on the v pp pin 10 - - ma t vpp (3) cumulative time during which v pp is applied - - 1 hour 1. guaranteed by design. 2. the maximum programming time is m easured after 100k erase operations. 3. v pp should only be connected du ring programming/erasing. symbol parameter conditions value unit min (1) 1. guaranteed by characterization. n end endurance t a = ?40 to +85 c (6 suffix versions) t a = ?40 to +105 c (7 suffix versions) 10 kcycles t ret data retention 1 kcycle (2) at t a = 85 c 2. cycling performed over the whole temperature range. 30 years 1 kcycle (2) at t a = 105 c 10 10 kcycles (2) at t a = 55 c 20 table 46. flash memory programming with v pp voltage (continued) symbol parameter conditions min (1) typ max (1) unit docid024738 rev 6 86/135 stm32f401xb stm32f401xc electrical characteristics 113 when the application is exposed to a noisy environment, it is recommended to avoid pin exposition to disturbances. the pins showing a middle range robustness are: pa0, pa1, pa2, on lqfp100 packages and pdr_on on wlcsp49. as a consequence, it is recommended to add a serial resistor (1 k maximum) located as close as possible to the mcu to the pins expo sed to noise (connected to tracks longer than 50 mm on pcb). designing hardened software to avoid noise problems emc characterization and optimization are per formed at component level with a typical application environment and simplified mcu soft ware. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in re lation with the emc level requested for his application. software recommendations the software flowchart must include the m anagement of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forci ng a low state on the nrst pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applie d directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). table 48. ems characteristics for lqfp100 package symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 3.3 v, lqfp100, wlcsp49, t a =+25c, f hclk = 84 mhz, conforms to iec 61000-4-2 2b v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd = 3.3 v, lqfp100, wlcsp49, t a =+25c, f hclk = 84 mhz, conforms to iec 61000-4-4 4a electrical characteristics stm32f401xb stm32f401xc 87/135 docid024738 rev 6 electromagnetic interference (emi) the electromagnetic field emitted by the device are monitored while a simple application, executing eembc code, is running. this emission test is compliant with sae iec61967-2 standard which specifies the test board and the pin loading. 6.3.14 absolute maximum ratings (electrical sensitivity) based on three different tests (esd, lu) using specific measurement methods, the device is stressed in order to determ ine its performance in terms of electrical sensitivity. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combinati on. the sample size depends on the number of supply pins in the device (3 parts (n+1) supply pins). this test conforms to the jesd22-a114/c101 standard. table 49. emi characteristics for wlcsp49 symbol parameter conditions monitored frequency band max vs. [f hse /f cpu ] unit 25/84 mhz s emi peak level v dd = 3.3 v, t a = 25 c, conforming to iec61967-2 0.1 to 30 mhz -6 dbv 30 to 130 mhz -6 130 mhz to 1 ghz -10 sae emi level 1.5 - table 50. emi characteristics for lqfp100 symbol parameter conditions monitored frequency band max vs. [f hse /f cpu ] unit 25/84 mhz s emi peak level v dd = 3.3 v, t a = 25 c, conforming to iec61967-2 0.1 to 30 mhz 18 dbv 30 to 130 mhz 23 130 mhz to 1 ghz 12 sae emi level 3.5 - docid024738 rev 6 88/135 stm32f401xb stm32f401xc electrical characteristics 113 static latchup two complementary static te sts are required on six pa rts to assess the latchup performance: ? a supply overvoltage is applied to each power supply pin ? a current injection is applied to each input, output and configurable i/o pin these tests are compliant with eia/jesd 78a ic latchup standard. 6.3.15 i/o current in jection characteristics as a general rule, current injection to the i/o pins, due to external voltage below v ss or above v dd (for standard, 3 v-capable i/o pins) should be avoided during normal product operation. however, in order to give an indica tion of the robustness of the microcontroller in cases when abnormal injection ac cidentally happens, susceptib ility tests are pe rformed on a sample basis during device characterization. functional susceptibilty to i/o current injection while a simple application is executed on the device, the device is stressed by injecting current into the i/o pins programmed in floating input mode . while current is injected into the i/o pin, one at a time, the device is checked for functional failures. the failure is indicated by an out of range parameter: adc error above a certain limit (>5 lsb tue), out of conventional limits of induced leakage current on adjacent pins (out of ?5 a/+0 a range), or other functional fa ilure (for example reset, oscillator frequency deviation). negative induced leakage current is caused by negative injection and positive induced leakage current by positive injection. the test results are given in table 53 . table 51. esd absolute maximum ratings symbol ratings conditions class maximum value (1) unit v esd(hbm) electrostatic discharge voltage (human body model) t a = +25 c conforming to jesd22- a114 2 2000 v v esd(cdm) electrostatic discharge voltage (charge device model) t a = +25 c conforming to ansi/esd stm5.3.1 ii 500 1. guaranteed by characterization. table 52. electrical sensitivities symbol parameter conditions class lu static latch-up class t a = +105 c conforming to jesd78a ii level a electrical characteristics stm32f401xb stm32f401xc 89/135 docid024738 rev 6 note: it is recommended to add a schottky diode (pin to ground) to analog pins which may potentially inject negative currents. 6.3.16 i/o port characteristics general input/output characteristics unless otherwise specified, the parameters given in table 54 are derived from tests performed under the conditions summarized in table 14 . all i/os are cmos and ttl compliant. table 53. i/o current injection susceptibility (1) 1. na = not applicable . symbol description functional susceptibility unit negative injection positive injection i inj injected current on boot0 pin ?0 na ma injected current on nrst pin ?0 na injected current on pb3, pb4, pb5, pb6, pb7, pb8, pb9, pc13, pc14, pc15, ph1, pdr_on, pc0, pc1,pc2, pc3, pd1, pd5, pd6, pd7, pe0, pe2, pe3, pe4, pe5, pe6 ?0 na injected current on any other ft pin ?5 na injected current on any other pins ?5 +5 table 54. i/o static characteristics symbol parameter conditions min typ max unit v il ft, and nrst i/o input low level voltage 1.7 v v dd 3.6 v - - 0.35v dd ?0.04 (1) v 0.3v dd (2) boot0 i/o input low level voltage 1.75 v v dd 3.6 v, -40 c t a 105 c -- 0.1v dd +0.1 1.7 v v dd 3.6 v, 0c t a 105 c -- v ih ft and nrst i/o input high level voltage (5) 1.7 v v dd 3.6 v 0.7v dd (1) -- v boot0 i/o input high level voltage 1.75 v v dd 3.6 v, -40 c t a 105 c 0.17v dd +0.7 (2) -- 1.7 v v dd 3.6 v, 0c t a 105 c docid024738 rev 6 90/135 stm32f401xb stm32f401xc electrical characteristics 113 all i/os are cmos and ttl compliant (no software configuration required). their characteristics cover more than the strict cmos-technology or ttl parameters. the coverage of these requirements for ft i/os is shown in figure 30 . v hys ft and nrst i/o input hysteresis 1.7 v v dd 3.6 v - 10% v dd (3) -v boot0 i/o input hysteresis 1.75 v v dd 3.6 v, -40 c t a 105 c -100 - mv 1.7 v v dd 3.6 v, 0c t a 105 c i lkg i/o input leakage current (4) v ss v in v dd -- 1 a i/o ft input leakage current (5) v in = 5v - - 3 r pu weak pull-up equivalent resistor (6) all pins except for pa10 (otg_fs_id ) v in = v ss 30 40 50 k pa10 (otg_fs_id ) 710 14 r pd weak pull-down equivalent resistor (7) all pins except for pa10 (otg_fs_id ) v in = v dd 30 40 50 pa10 (otg_fs_id ) 710 14 c io (8) i/o pin capacitance - - 5 - pf 1. guaranteed by design. 2. guaranteed by test in production. 3. with a minimum of 200 mv. 4. leakage could be higher than the maximum value, if negat ive current is injected on adjacent pins, refer to table 53: i/o current injection susceptibility 5. to sustain a voltage higher than vdd +0.3 v, the internal pull-up/pull-down resistors mu st be disabled. leakage could be higher than the maximum value, if negative curr ent is injected on adjacent pins.refer to table 53: i/o current injection susceptibility 6. pull-up resistors are designed with a true resistance in se ries with a switchable pmos. this pmos contribution to the series resistance is minimum (~10% order). 7. pull-down resistors are designed with a true resistance in se ries with a switchable nmos. th is nmos contribution to the series resistance is minimum (~10% order). 8. hysteresis voltage between schmitt trigger sw itching levels. guaranteed by characterization. table 54. i/o static characteristics (continued) symbol parameter conditions min typ max unit electrical characteristics stm32f401xb stm32f401xc 91/135 docid024738 rev 6 figure 30. ft i/o input characteristics output driving current the gpios (general purpose input/outputs) can sink or source up to 8 ma, and sink or source up to 20 ma (with a relaxed v ol /v oh ) except pc13, pc14 and pc15 which can sink or source up to 3ma. when using the pc13 to pc15 gpios in output mode, the speed should not exceed 2 mhz with a maximum load of 30 pf. in the user application, the number of i/o pi ns which can drive curr ent must be limited to respect the absolute maximum rating specified in section 6.2 . in particular: ? the sum of the currents sourced by all the i/os on v dd, plus the maximum run consumption of the mcu sourced on v dd, cannot exceed the absolute maximum rating i vdd (see table 12 ). ? the sum of the currents sunk by all the i/os on v ss plus the maximum run consumption of the mcu sunk on v ss cannot exceed the absolute maximum rating i vss (see table 12 ). output voltage levels unless otherwise specified, the parameters given in table 55 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 14 . all i/os are cmos and ttl compliant. 0 6 9 9 ' ' 9 9 , / 9 , + 9 7 h v w h g l q s u r g x f w l r q & 0 2 6 u h t x l u h p h q w 9 , + p l q 9 ' ' 7 h v w h g l q s u r g x f w l r q & 0 2 6 u h t x l u h p h q w 9 , / p d [ 9 ' ' % d v h g r q ' h v l j q v l p x o d w l r q v 9 , / p d [ 9 ' ' 7 7 / u h t x l u h p h q w 9 , + p l q 9 7 7 / u h t x l u h p h q w 9 , / p d [ 9 $ u h d q r w g h w h u p l q h g % d v h g r q ' h v l j q v l p x o d w l r q v 9 , + p l q 9 ' ' docid024738 rev 6 92/135 stm32f401xb stm32f401xc electrical characteristics 113 input/output ac characteristics the definition and values of input/output ac characteristics are given in figure 31 and table 56 , respectively. unless otherwise specified, the parameters given in table 56 are derived from tests performed under the ambient temperature and v dd supply voltage conditions summarized in table 14 . table 55. output voltage characteristics symbol parameter conditions min max unit v ol (1) 1. the i io current sunk by the device must always res pect the absolute maximum rating specified in table 12 . and the sum of i io (i/o ports and control pins) must not exceed i vss . output low level voltage for an i/o pin cmos port (2) i io = +8 ma 2.7 v v dd 3.6 v 2. ttl and cmos outputs are compatible with jedec standards jesd36 and jesd52. -0.4 v v oh (3) 3. the i io current sourced by the device must always re spect the absolute maximum rating specified in table 12 and the sum of i io (i/o ports and control pins) must not exceed i vdd . output high level voltage for an i/o pin v dd ?0.4 - v ol (1) output low level voltage for an i/o pin ttl port (2) i io =+8 ma 2.7 v v dd 3.6 v -0.4 v v oh (3) output high level voltage for an i/o pin 2.4 - v ol (1) output low level voltage for an i/o pin i io = +20 ma 2.7 v v dd 3.6 v -1.3 (4) 4. guaranteed by characterization. v v oh (3) output high level voltage for an i/o pin v dd ?1.3 (4) - v ol (1) output low level voltage for an i/o pin i io = +6 ma 1.8 v v dd 3.6 v -0.4 (4) v v oh (3) output high level voltage for an i/o pin v dd ?0.4 (4) - v ol (1) output low level voltage for an i/o pin i io = +4 ma 1.7 v v dd 3.6 v -0.4 (5) 5. guaranteed by design. v v oh (3) output high level voltage for an i/o pin v dd ?0.4 (5) - table 56. i/o ac characteristics (1)(2) ospeedry [1:0] bit value (1) symbol parameter conditions min typ max unit 00 f max(io)out maximum frequency (3) c l = 50 pf, v dd 2.70 v - - 4 mhz c l = 50 pf, v dd 1.7 v - - 2 c l = 10 pf, v dd 2.70 v - - 8 c l = 10 pf, v dd 1.7 v - - 4 t f(io)out / t r(io)out output high to low level fall time and output low to high level rise time c l = 50 pf, v dd = 1.7 v to 3.6 v --100ns electrical characteristics stm32f401xb stm32f401xc 93/135 docid024738 rev 6 01 f max(io)out maximum frequency (3) c l = 50 pf, v dd 2.70 v - - 25 mhz c l = 50 pf, v dd 1.7 v - - 12.5 c l = 10 pf, v dd 2.70 v - - 50 c l = 10 pf, v dd 1.7 v - - 20 t f(io)out / t r(io)out output high to low level fall time and output low to high level rise time c l = 50 pf, v dd 2.7 v - - 10 ns c l = 50 pf, v dd 1.7 v - - 20 c l = 10 pf, v dd 2.70 v - - 6 c l = 10 pf, v dd 1.7 v - - 10 10 f max(io)out maximum frequency (3) c l = 40 pf, v dd 2.70 v - - 50 (4) mhz c l = 40 pf, v dd 1.7 v - - 25 c l = 10 pf, v dd 2.70 v - - 100 (4) c l = 10 pf, v dd 1.7 v - - 50 (4) t f(io)out / t r(io)out output high to low level fall time and output low to high level rise time c l = 40 pf, v dd 2.70 v - - 6 ns c l = 40 pf, v dd 1.7 v - - 10 c l = 10 pf, v dd 2.70 v - - 4 c l = 10 pf, v dd 1.7 v - - 6 11 f max(io)out maximum frequency (3) c l = 30 pf, v dd 2.70 v - - 100 (4) mhz c l = 30 pf, v dd 1.7 v - - 50 (4) c l = 10 pf, v dd 2.70 v - - 180 (4) c l = 10 pf, v dd 1.7 v - - 100 (4) t f(io)out / t r(io)out output high to low level fall time and output low to high level rise time c l = 30 pf, v dd 2.70 v - - 4 ns c l = 30 pf, v dd 1.7 v - - 6 c l = 10 pf, v dd 2.70 v - - 2.5 c l = 10 pf, v dd 1.7 v - - 4 -t extipw pulse width of external signals detected by the exti controller 10 - - ns 1. guaranteed by characterization. 2. the i/o speed is configured using the ospeedry[1:0] bits. refer to the stm32f4xx reference manual for a description of the gpiox_speedr gpio port output speed register. 3. the maximum frequency is defined in figure 31 . 4. for maximum frequencies above 50 mhz and v dd > 2.4 v, the compensation cell should be used. table 56. i/o ac characteristics (1)(2) (continued) ospeedry [1:0] bit value (1) symbol parameter conditions min typ max unit docid024738 rev 6 94/135 stm32f401xb stm32f401xc electrical characteristics 113 figure 31. i/o ac charac teristics definition 6.3.17 nrst pin characteristics the nrst pin input driver uses cmos technology. it is connected to a permanent pull-up resistor, r pu (see table 54 ). unless otherwise specified, the parameters given in table 57 are derived from tests performed under the ambient temperature and v dd supply voltage conditions summarized in table 14 . refer to table 54: i/o static characteristics for the values of vih and vil for nrst pin. d l g w u , 2 r x w 2 8 7 3 8 7 ( ; 7 ( 5 1 $ / 2 1 & / 0 d [ l p x p i u h t x h q f \ l v d f k l h y h g l i w u w i ? 7 d q g l i w k h g x w \ f \ f o h l v z k h q o r d g h g e \ & / v s h f l i l h g l q w k h w d e o h 3 , 2 $ & f k d u d f w h u l v w l f v 7 w i , 2 r x w table 57. nrst pin characteristics symbol parameter conditions min typ max unit r pu weak pull-up equivalent resistor (1) v in = v ss 30 40 50 k v f(nrst) (2) nrst input filtered pulse - - 100 ns v nf(nrst) (2) nrst input not filtered pulse v dd > 2.7 v 300 - - ns t nrst_out generated reset pulse duration internal reset source 20 - - s 1. the pull-up is designed with a true re sistance in series with a switchable pmos . this pmos contribution to the series resistance must be minimum (~10% order) . 2. guaranteed by design. electrical characteristics stm32f401xb stm32f401xc 95/135 docid024738 rev 6 figure 32. recommended nrst pin protection 1. the reset network protects t he device against par asitic resets. 2. the external capacitor must be placed as close as possibl e to the device. 3. the user must ensure that the level on the nrst pin can go below the v il(nrst) max level specified in table 57 . otherwise the reset is not taken into account by the device. 6.3.18 tim time r characteristics the parameters given in table 58 are guaranteed by design. refer to section 6.3.16: i/o port characteristics for details on the input/output alternate function characteristics (output compare, i nput capture, external clock, pwm output). d l f 6 7 0 ) 5 3 8 1 5 6 7 9 ' ' ) l o w h u , q w h u q d o 5 h v h w ? ) ( [ w h u q d o u h v h w f l u f x l w table 58. timx characteristics (1)(2) 1. timx is used as a general term to refer to the tim1 to tim11 timers. 2. guaranteed by design. symbol parameter conditions (3) 3. the maximum timer frequency on apb1 is 42 mhz and on apb2 is up to 84 mhz, by setting the timpre bit in the rcc_dckcfgr register, if apbx prescaler is 1 or 2 or 4, then timxclk = hckl, otherwise timxclk >= 4x pclkx. min max unit t res(tim) timer resolution time ahb/apbx prescaler=1 or 2 or 4, f timxclk = 84 mhz 1- t timxclk 11.9 - ns ahb/apbx prescaler>4, f timxclk = 84 mhz 1- t timxclk 11.9 - ns f ext timer external clock frequency on ch1 to ch4 f timxclk = 84 mhz 0 f timxclk /2 mhz 042mhz res tim timer resolution - 16/32 bit t counter 16-bit counter clock period when internal clock is selected f timxclk = 84 mhz 0.0119 780 s t max_count maximum possible count with 32-bit counter - 65536 65536 t timxclk f timxclk = 84 mhz -51.1s docid024738 rev 6 96/135 stm32f401xb stm32f401xc electrical characteristics 113 6.3.19 communications interfaces i 2 c interface characteristics the i 2 c interface meets the requirements of the standard i 2 c communication protocol with the following restrictions: the i/o pins sda and scl are mapped to are not ?true? open- drain. when configured as open-drain, the pmos connected between the i/o pin and v dd is disabled, but is still present. the i 2 c characteristics are described in table59 . refer also to section 6.3.16: i/o port characteristics for more details on the input/output al ternate function characteristics (sda and scl). the i 2 c bus interface supports standard mode (u p to 100 khz) and fast mode (up to 400 khz). the i 2 c bus frequency can be increased up to 1 mhz. for more details about the complete solution, please contact your local st sales representative. table 59. i 2 c characteristics symbol parameter standard mode i 2 c (1) fast mode i 2 c (1)(2) unit min max min max t w(scll) scl clock low time 4.7 - 1.3 - s t w(sclh) scl clock high time 4.0 - 0.6 - t su(sda) sda setup time 250 - 100 - ns t h(sda) sda data hold time 0 - 0 900 (3) t r(sda) t r(scl) sda and scl rise time - 1000 - 300 t f(sda) t f(scl) sda and scl fall time - 300 - 300 t h(sta) start condition hold time 4.0 - 0.6 - s t su(sta) repeated start condition setup time 4.7 - 0.6 - t su(sto) stop condition setup time 4.0 - 0.6 - s t w(sto:sta) stop to start condition time (bus free) 4.7 - 1.3 - s t sp pulse width of the spikes that are suppressed by the analog filter for standard fast mode 050 (4) 050 (4) ns c b capacitive load for each bus line - 400 - 400 pf 1. guaranteed by design. 2. f pclk1 must be at least 2 mhz to achieve standard mode i 2 c frequencies. it must be at leas t 4 mhz to achieve fast mode i 2 c frequencies, and a multiple of 10 mhz to reach the 400 khz maximum i 2 c fast mode clock. 3. the maximum data hold time has only to be met if the interface does not stretch the low period of scl signal. 4. the minimum width of the spikes fi ltered by the analog filter is above t sp (max). electrical characteristics stm32f401xb stm32f401xc 97/135 docid024738 rev 6 figure 33. i 2 c bus ac waveforms and measurement circuit 1. r s = series protection resistor. 2. r p = external pull-up resistor. 3. v dd_i2c is the i2c bus power supply. table 60. scl frequency (f pclk1 = 42 mhz, v dd = v dd_i2c = 3.3 v) (1)(2) 1. r p = external pull-up resistance, f scl = i 2 c speed 2. for speeds around 200 khz, the tole rance on the achieved speed is of 5%. for other speed ranges, the tolerance on the achieved speed is 2%. these variations depend on the accuracy of the external components used to design the application. f scl (khz) i2c_ccr value r p = 4.7 k 400 0x8019 300 0x8021 200 0x8032 100 0x0096 50 0x012c 20 0x02ee d l f 5 3 , e & e x v s ' ' b , & 6 7 0 ) [ [ 6 ' $ 6 & / w i 6 ' $ w u 6 ' $ w k 6 7 $ w z 6 & / / w z 6 & / + w v x 6 ' $ w u 6 & / w i 6 & / w k 6 ' $ 6 7 $ 5 7 5 ( 3 ( $ 7 ( ' w v x 6 7 $ w v x 6 7 2 6 7 2 3 w z 6 7 2 6 7 $ s ' ' b , & 5 3 5 6 5 6 6 7 $ 5 7 6 7 $ 5 7 6 ' $ 6 & / docid024738 rev 6 98/135 stm32f401xb stm32f401xc electrical characteristics 113 spi interface characteristics unless otherwise specified, the parameters given in table 61 for the spi interface are derived from tests performed under the ambient temperature, f pclkx frequency and v dd supply voltage conditions summarized in table 14 , with the following configuration: ? output speed is set to ospeedry[1:0] = 10 ? capacitive load c = 30 pf ? measurement points are done at cmos levels: 0.5v dd refer to section 6.3.16: i/o port characteristics for more details on the input/output alternate function characteristics (nss, sck, mosi, miso for spi). table 61. spi dynamic characteristics (1) symbol parameter conditions min typ max unit f sck 1/t c(sck) spi clock frequency master mode, spi1/4, 2.7 v < v dd <3.6v -- 42 mhz slave mode, spi1/4, 2.7 v < v dd <3.6v 42 slave transmitter/full-duplex mode, spi1/4, 2.7 v < v dd <3.6v 38 (2) master mode, spi1/2/3/4, 1.7 v < v dd <3.6v 21 slave mode, spi1/2/3/4, 1.7 v < v dd <3.6v 21 duty(sck) duty cycle of spi clock frequency slave mode 30 50 70 % t w(sckh) t w(sckl) sck high and low time master mode, spi presc = 2 t pclk ? 1.5 t pclk t pclk +1.5 ns t su(nss) nss setup time slave mode, spi presc = 2 4 t pclk --ns t h(nss) nss hold time slave mode, spi presc = 2 2 t pclk --ns t su(mi) data input setup time master mode 0 - - ns t su(si) slave mode 2.5 - - ns t h(mi) data input hold time master mode 6 - - ns t h(si) slave mode 2.5 - - ns t a(so ) data output access time slave mode 9 - 20 ns t dis(so) data output disable time slave mode 8 - 13 ns t v(so) data output valid time slave mode (after enable edge), 2.7 v < v dd < 3.6 v -9.513ns slave mode (after enable edge), 1.7 v < v dd < 3.6 v -9.517ns t h(so) data output hold time slave mode (after enable edge), 2.7 v < v dd < 3.6 v 5.5 - - ns slave mode (after enable edge), 1.7 v < v dd < 3.6 v 3.5 - - ns electrical characteristics stm32f401xb stm32f401xc 99/135 docid024738 rev 6 figure 34. spi timing diagram - slave mode and cpha = 0 figure 35. spi timing diagram - slave mode and cpha = 1 (1) t v(mo) data output valid time master mode (after enable edge) - 3 5 ns t h(mo) data output hold time master mode (after enable edge) 2 - - ns 1. guaranteed by characterization. 2. maximum frequency in slav e transmitter mode is determined by the sum of t v(so) and t su(mi) which has to fit into sck low or high phase preceding the sck sampling edge. this value can be achieved when the spi communicates with a master having t su(mi) = 0 while duty(sck) = 50% table 61. spi dynamic characteristics (1) (continued) symbol parameter conditions min typ max unit 0 6 y 9 1 6 6 l q s x w & 3 + $ & 3 2 / 6 & . l q s x w & 3 + $ & 3 2 / 0 , 6 2 r x w s x w 0 2 6 , l q s x w w v x 6 , w k 6 , w z 6 & . / w z 6 & . + w f 6 & . w u 6 & . w k 1 6 6 w g l v 6 2 w v x 1 6 6 w d 6 2 w y 6 2 1 h [ w e l w v , 1 / d v w e l w 2 8 7 ) l u v w e l w , 1 ) l u v w e l w 2 8 7 1 h [ w e l w v 2 8 7 w k 6 2 w i 6 & . / d v w e l w , 1 0 6 y 9 1 6 6 l q s x w & 3 + $ & 3 2 / 6 & . l q s x w & 3 + $ & 3 2 / 0 , 6 2 r x w s x w 0 2 6 , l q s x w w v x 6 , w k 6 , w z 6 & . / w z 6 & . + w v x 1 6 6 w f 6 & . w d 6 2 w y 6 2 ) l u v w e l w 2 8 7 1 h [ w e l w v 2 8 7 1 h [ w e l w v , 1 / d v w e l w 2 8 7 w k 6 2 w u 6 & . w i 6 & . w k 1 6 6 w g l v 6 2 ) l u v w e l w , 1 / d v w e l w , 1 docid024738 rev 6 100/135 stm32f401xb stm32f401xc electrical characteristics 113 figure 36. spi timing diagram - master mode (1) d l f 6 & . 2 x w s x w & 3 + $ 0 2 6 , 2 8 7 3 8 7 0 , 6 2 , 1 3 8 7 & 3 + $ / 6 % 2 8 7 / 6 % , 1 & 3 2 / & 3 2 / % , 7 2 8 7 1 6 6 l q s x w w f 6 & . w z 6 & . + w z 6 & . / w u 6 & . w i 6 & . w k 0 , + l j k 6 & . 2 x w s x w & 3 + $ & 3 + $ & 3 2 / & 3 2 / w v x 0 , w y 0 2 w k 0 2 0 6 % , 1 % , 7 , 1 0 6 % 2 8 7 electrical characteristics stm32f401xb stm32f401xc 101/135 docid024738 rev 6 i 2 s interface characteristics unless otherwise specified, the parameters given in table 62 for the i 2 s interface are derived from tests performed under the ambient temperature, f pclkx frequency and v dd supply voltage conditions summarized in table 14 , with the following configuration: ? output speed is set to ospeedry[1:0] = 10 ? capacitive load c = 30 pf ? measurement points are done at cmos levels: 0.5v dd refer to section 6.3.16: i/o port characteristics for more details on the input/output alternate function characteristics (ck, sd, ws). note: refer to the i2s section of the reference manual for more details on the sampling frequency (f s ). f mck , f ck , and d ck values reflect only the digital peripheral behavior. the values of these parameters might be slightly impacted by the source clock precision. d ck depends mainly on the value of odd bit. the digital contribution leads to a minimum value of (i2sdiv/(2*i2sdiv+odd) and a maximum va lue of (i2sdiv+odd) /(2*i2sdiv+odd). f s maximum value is supported for each mode/condition. table 62. i 2 s dynamic characteristics (1) symbol parameter conditions min max unit f mck i2s main clock output - 256x8k 256xfs (2) mhz f ck i2s clock frequency master data: 32 bits - 64xfs mhz slave data: 32 bits - 64xfs d ck i2s clock frequency duty cycle slave receiver 30 70 % t v(ws) ws valid time master mode 0 6 ns t h(ws) ws hold time master mode 0 - t su(ws) ws setup time slave mode 1 - t h(ws) ws hold time slave mode 0 - t su(sd_mr) data input setup time master receiver 7.5 - t su(sd_sr) slave receiver 2 - t h(sd_mr) data input hold time master receiver 0 - t h(sd_sr) slave receiver 0 - t v(sd_st) t h(sd_st) data output valid time slave transmitter (after enable edge) - 27 t v(sd_mt) master transmitter (after enable edge) - 20 t h(sd_mt) data output hold time master tr ansmitter (after enable edge) 2.5 - 1. guaranteed by characterization. 2. the maximum value of 256xfs is 42 mhz (apb1 maximum frequency). docid024738 rev 6 102/135 stm32f401xb stm32f401xc electrical characteristics 113 figure 37. i 2 s slave timing diagram (philips protocol) (1) 1. lsb transmit/receive of the previ ously transmitted byte. no lsb transmi t/receive is sent before the first byte. figure 38. i 2 s master timing diagram (philips protocol) (1) 1. lsb transmit/receive of the previ ously transmitted byte. no lsb transmi t/receive is sent before the first byte. ck input cpol = 0 cpol = 1 t c(ck) ws input sd transmit sd receive t w(ckh) t w(ckl) t su(ws) t v(sd_st) t h(sd_st) t h(ws) t su(sd_sr) t h(sd_sr) msb receive bitn receive lsb receive msb transmit bitn transmit lsb transmit ai14881b lsb receive (2) lsb transmit (2) ck output cpol = 0 cpol = 1 t c(ck) ws output sd receive sd transmit t w(ckh) t w(ckl) t su(sd_mr) t v(sd_mt) t h(sd_mt) t h(ws) t h(sd_mr) msb receive bitn receive lsb receive msb transmit bitn transmit lsb transmit ai14884b t f(ck) t r(ck) t v(ws) lsb receive (2) lsb transmit (2) electrical characteristics stm32f401xb stm32f401xc 103/135 docid024738 rev 6 usb otg full speed (fs) characteristics this interface is present in usb otg fs controller. note: when vbus sensing feature is enabled, pa9 shou ld be left at their default state (floating input), not as alternate function. a typical 200 a current consumption of the embedded sensing block (current to voltage conversion to determine the different sessions) can be observed on pa9 when the feature is enabled. table 63. usb otg fs startup time symbol parameter max unit t startup (1) 1. guaranteed by design. usb otg fs transceiver startup time 1 s table 64. usb otg fs dc electrical characteristics symbol parameter conditions min. (1) 1. all the voltages are measured from the local ground potential. typ. max. (1) unit input levels v dd usb otg fs operating voltage 3.0 (2) 2. the usb otg fs functionality is ensured down to 2.7 v but not the full usb full speed electrical characteristics which are degraded in the 2.7-to-3.0 v v dd voltage range. -3.6v v di (3) 3. guaranteed by design. differential input sensitivity i(usb_fs_dp/dm) 0.2 - - v v cm (3) differential common mode range includes v di range 0.8 - 2.5 v se (3) single ended receiver threshold 1.3 - 2.0 output levels v ol static output level low r l of 1.5 k to 3.6 v (4) 4. r l is the load connected on the usb otg fs drivers. --0.3 v v oh static output level high r l of 15 k to v ss (4) 2.8 - 3.6 r pd pa11, pa12 (usb_fs_dm/dp) v in = v dd 17 21 24 k pa9 (otg_fs_vbus) 0.65 1.1 2.0 r pu pa11, pa12 (usb_fs_dm/dp) v in = v ss 1.5 1.8 2.1 pa9 (otg_fs_vbus) v in = v ss 0.25 0.37 0.55 docid024738 rev 6 104/135 stm32f401xb stm32f401xc electrical characteristics 113 figure 39. usb otg fs timings: definiti on of data signal rise and fall time 6.3.20 12-bit adc characteristics unless otherwise specified, the parameters given in table 66 are derived from tests performed under the ambient temperature, f pclk2 frequency and v dda supply voltage conditions su mmarized in table 14 . table 65. usb otg fs el ectrical characteristics (1) 1. guaranteed by design. driver characteristics symbol parameter conditions min max unit t r rise time (2) 2. measured from 10% to 90% of the data signal. for more detailed informations, please refer to usb specification - chapter 7 (version 2.0). c l = 50 pf 420ns t f fall time (2) c l = 50 pf 4 20 ns t rfm rise/ fall time matching t r /t f 90 110 % v crs output signal crossover voltage 1.3 2.0 v a i14137 t f differen ti a l d a t a line s v ss v cr s t r cro ss over point s table 66. adc characteristics symbol parameter conditions min typ max unit v dda power supply v dda ? v ref+ < 1.2 v 1.7 (1) -3.6 v v ref+ positive reference voltage 1.7 (1) -v dda v ref- negative reference voltage - - 0 - f adc adc clock frequency v dda = 1.7 (1) to 2.4 v 0.6 15 18 mhz v dda = 2.4 to 3.6 v 0.6 30 36 mhz f trig (2) external trigger frequency f adc = 30 mhz, 12-bit resolution - - 1764 khz --171/f adc v ain conversion voltage range (3) 0 (v ssa or v ref- tied to ground) -v ref+ v r ain (2) external input impedance see equation 1 for details --50k r adc (2)(4) sampling switch resistance - - 6 k c adc (2) internal sample and hold capacitor -47pf electrical characteristics stm32f401xb stm32f401xc 105/135 docid024738 rev 6 t lat (2) injection trigger conversion latency f adc = 30 mhz - - 0.100 s --3 (5) 1/f adc t latr (2) regular trigger conversion latency f adc = 30 mhz - - 0.067 s --2 (5) 1/f adc t s (2) sampling time f adc = 30 mhz 0.100 - 16 s 3 - 480 1/f adc t stab (2) power-up time - 2 3 s t conv (2) total conversion time (including sampling time) f adc = 30 mhz 12-bit resolution 0.50 - 16.40 s f adc = 30 mhz 10-bit resolution 0.43 - 16.34 s f adc = 30 mhz 8-bit resolution 0.37 - 16.27 s f adc = 30 mhz 6-bit resolution 0.30 - 16.20 s 9 to 492 (t s for sampling +n-bit re solution for successive approximation) 1/f adc f s (2) sampling rate (f adc = 30 mhz, and t s = 3 adc cycles) 12-bit resolution single adc - - 2 msps 12-bit resolution interleave dual adc mode - - 3.75 msps 12-bit resolution interleave triple adc mode - - 6 msps i vref+ (2) adc v ref dc current consumption in conversion mode - 300 500 a i vdda (2) adc v dda dc current consumption in conversion mode -1.61.8ma 1. v dda minimum value of 1.7 v is possible with the use of an external power suppl y supervisor (refer to section 3.14.2: internal reset off ). 2. guaranteed by characterization. 3. v ref+ is internally connected to v dda and v ref- is internally connected to v ssa . 4. r adc maximum value is given for v dd =1.7 v, and minimum value for v dd =3.3 v. 5. for external triggers, a delay of 1/f pclk2 must be added to the latency specified in table 66 . table 66. adc characteristics (continued) symbol parameter conditions min typ max unit docid024738 rev 6 106/135 stm32f401xb stm32f401xc electrical characteristics 113 equation 1: r ain max formula the formula above ( equation 1 ) is used to dete rmine the maximum external impedance allowed for an error below 1/4 of lsb. n = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the adc_smpr1 register. table 67. adc accuracy at f adc = 18 mhz symbol parameter test conditions typ max (1) 1. guaranteed by characterization. unit et total unadjusted error f adc =18 mhz v dda = 1.7 to 3.6 v v ref = 1.7 to 3.6 v v dda ? v ref < 1.2 v 3 4 lsb eo offset error 2 3 eg gain error 1 3 ed differential linearity error 1 2 el integral linearity error 2 3 table 68. adc accuracy at f adc = 30 mhz symbol parameter test conditions typ max (1) 1. guaranteed by characterization. unit et total unadjusted error f adc = 30 mhz, r ain < 10 k , v dda = 2.4 to 3.6 v, v ref = 1.7 to 3.6 v, v dda ? v ref < 1.2 v 2 5 lsb eo offset error 1.5 2.5 eg gain error 1.5 3 ed differential linearity error 1 2 el integral linearity error 1.5 3 table 69. adc accuracy at f adc = 36 mhz symbol parameter test conditions typ max (1) 1. guaranteed by characterization. unit et total unadjusted error f adc =36 mhz, v dda = 2.4 to 3.6 v, v ref = 1.7 to 3.6 v v dda ? v ref < 1.2 v 4 7 lsb eo offset error 2 3 eg gain error 3 6 ed differential linearity error 2 3 el integral linearity error 3 6 r ain k0.5 ? () f adc c adc 2 n 2 + () ln ---------------------------------------------------------------- r adc ? = electrical characteristics stm32f401xb stm32f401xc 107/135 docid024738 rev 6 note: adc accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this signifi cantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to analog pins which may potentially inject negative currents. any positive injection current within the limits specified for i inj(pin) and i inj(pin) in section 6.3.16 does not affect the adc accuracy. table 70. adc dynamic accuracy at f adc = 18 mhz - limited test conditions (1) 1. guaranteed by characterization. symbol parameter test conditions min typ max unit enob effective number of bits f adc =18 mhz v dda = v ref+ = 1.7 v input frequency = 20 khz temperature = 25 c 10.3 10.4 - bits sinad signal-to-noise and distortion ratio 64 64.2 - db snr signal-to-noise ratio 64 65 - thd total harmonic distortion - 67 - 72 - table 71. adc dynamic accuracy at f adc = 36 mhz - limited test conditions (1) 1. guaranteed by characterization. symbol parameter test conditions min typ max unit enob effective number of bits f adc = 36 mhz v dda = v ref+ = 3.3 v input frequency = 20 khz temperature = 25 c 10.6 10.8 - bits sinad signal-to noise and distortion ratio 66 67 - db snr signal-to noise ratio 64 68 - thd total harmonic distortion - 70 - 72 - docid024738 rev 6 108/135 stm32f401xb stm32f401xc electrical characteristics 113 figure 40. adc accuracy characteristics 1. see also table 68 . 2. example of an actual transfer curve. 3. ideal transfer curve. 4. end point correlation line. 5. e t = total unadjusted error: maximum deviation be tween the actual and the ideal transfer curves. eo = offset error: deviation between the fi rst actual transition and the first ideal one. eg = gain error: deviation between the last ideal transition and the last actual one. ed = differential linearity error: maximum deviation between actual steps and the ideal one. el = integral linearity error: maximum deviati on between any actual transition and the end point correlation line. figure 41. typical connecti on diagram using the adc 1. refer to table 66 for the values of r ain , r adc and c adc . 2. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad capacitance (roughly 5 pf). a high c parasitic value downgrades conversion accuracy. to remedy this, f adc should be reduced. a i c % / % ' , 3 " ) $ % ! , % 4 % $ % , 6 $ $ ! 6 3 3 ! 6 2 % & o r d e p e n d i n g o n p a c k a g e = 6 $ $ ! ; , 3 " ) $ % ! , d l 6 7 0 ) 9 ' ' $ , 1 [ , / ? ? $ 9 9 7 5 $ , 1 & s d u d v l w l f 9 $ , 1 9 9 7 5 $ ' & & $ ' & e l w f r q y h u w h u 6 d p s o h d q g k r o g $ ' & f r q y h u w h u electrical characteristics stm32f401xb stm32f401xc 109/135 docid024738 rev 6 general pcb design guidelines power supply decoupling should be performed as shown in figure 42 or figure 43 , depending on whether v ref+ is connected to v dda or not. the 10 nf capacitors should be ceramic (good quality). they should be placed them as close as possible to the chip. figure 42. power supply and reference decoupling (v ref+ not connected to v dda ) 1. v ref+ and v ref- inputs are both available on ufbga100. v ref+ is also available on lqfp100. when v ref+ and v ref- are not available, they ar e internally connected to v dda and v ssa . 6 7 0 ) ? ) q ) ? ) q ) 9 5 ( ) 9 ' ' $ 9 6 6 $ 9 5 ( ) d l e docid024738 rev 6 110/135 stm32f401xb stm32f401xc electrical characteristics 113 figure 43. power supply and reference decoupling (v ref+ connected to v dda ) 1. v ref+ and v ref- inputs are both available on ufbga100. v ref+ is also available on lqfp100. when v ref+ and v ref- are not available, they ar e internally connected to v dda and v ssa . 6.3.21 temperature sensor characteristics 6 7 0 ) ? ) q ) d l f 9 5 ( ) 9 ' ' $ 9 5 ( ) 9 6 6 $ table 72. temperature sensor characteristics symbol parameter min typ max unit t l (1) v sense linearity with temperature - 1 2c avg_slope (1) average slope - 2.5 - mv/c v 25 (1) voltage at 25 c - 0.76 - v t start (2) startup time - 6 10 s t s_temp (2) adc sampling time when reading the temperature (1 c accuracy) 10 - - s 1. guaranteed by characterization. 2. guaranteed by design. table 73. temperature sensor calibration values symbol parameter memory address ts_cal1 ts adc raw data acquired at temperature of 30 c, v dda = 3.3 v 0x1fff 7a2c - 0x1fff 7a2d ts_cal2 ts adc raw data acquired at temperature of 110 c, v dda = 3.3 v 0x1fff 7a2e - 0x1fff 7a2f electrical characteristics stm32f401xb stm32f401xc 111/135 docid024738 rev 6 6.3.22 v bat monitoring characteristics 6.3.23 embedded reference voltage the parameters given in table 75 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 14 . 6.3.24 sd/sdio mmc card host in terface (sdio) characteristics unless otherwise specified, the parameters given in table 77 for the sdio/mmc interface are derived from tests performed under the ambient temperature, f pclk2 frequency and v dd supply voltage conditions summarized in table 14 , with the following configuration: ? output speed is set to ospeedry[1:0] = 10 ? capacitive load c = 30 pf ? measurement points are done at cmos levels: 0.5v dd table 74. v bat monitoring characteristics symbol parameter min typ max unit r resistor bridge for v bat -50-k q ratio on v bat measurement - 4 - er (1) error on q ?1 - +1 % t s_vbat (2)(2) adc sampling time when reading the v bat 1 mv accuracy 5- -s 1. guaranteed by design. 2. shortest sampling time can be determined in the application by multiple iterations. table 75. embedded internal reference voltage symbol parameter conditions min typ max unit v refint internal reference voltage ?40 c < t a < +105 c 1.18 1.21 1.24 v t s_vrefint (1) adc sampling time when reading the internal reference voltage -10--s v rerint_s (2) internal reference voltage spread over the temperature range v dd = 3v 10mv - 3 5 mv t coeff (2) temperature coefficient - - 30 50 ppm/c t start (2) startup time - - 6 10 s 1. shortest sampling time can be determined in the application by multiple iterations. 2. guaranteed by design. table 76. internal reference voltage calibration values symbol parameter memory address v refin_cal raw data acquired at temperature of 30 c v dda = 3.3 v 0x1fff 7a2a - 0x1fff 7a2b docid024738 rev 6 112/135 stm32f401xb stm32f401xc electrical characteristics 113 refer to section 6.3.16: i/o port characteristics for more details on the input/output characteristics. figure 44. sdio high-speed mode figure 45. sd default mode t w(ckh) ck d, cmd (o u tp u t) d, cmd (inp u t) t c t w(ckl) t ov t oh t i s u t ih t f t r a i14 88 7 ck d, cmd (o u tp u t) t ovd t ohd a i14 888 table 77. dynamic characteristics: sd / mmc characteristics (1)(2) symbol parameter conditions min typ max unit f pp clock frequency in data transfer mode 0 - 48 mhz - sdio_ck/fpclk2 frequency ratio - - 8/3 - t w(ckl) clock low time fpp = 48mhz 8.5 9 - ns t w(ckh) clock high time fpp = 48mhz 8.3 10 - cmd, d inputs (referenced to ck) in mmc and sd hs mode t isu input setup time hs fpp = 48mhz 3.5 - - ns t ih input hold time hs fpp = 48mhz 0 - - cmd, d outputs (referenced to ck) in mmc and sd hs mode t ov output valid time hs fpp = 48mhz - 4.5 7 ns t oh output hold time hs fpp = 48mhz 3 - - electrical characteristics stm32f401xb stm32f401xc 113/135 docid024738 rev 6 6.3.25 rtc characteristics cmd, d inputs (referenced to ck) in sd default mode t isud input setup time sd fpp = 24mhz 1.5 - - ns t ihd input hold time sd fpp = 24mhz 0.5 - - cmd, d outputs (referenced to ck) in sd default mode t ovd output valid default time sd fpp =24mhz - 4.5 6.5 ns t ohd output hold default time sd fpp =24mhz 3.5 - - 1. guaranteed by char acterization results. 2. v dd = 2.7 to 3.6 v. table 77. dynamic characteristic s: sd / mmc characteristics (1)(2) (continued) symbol parameter conditions min typ max unit table 78. rtc characteristics symbol parameter conditions min max -f pclk1 /rtcclk frequency ratio any read/write operation from/to an rtc register 4- docid024738 rev 6 114/135 stm32f401xb stm32f401xc package information 130 7 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark. 7.1 wlcsp49 2.965x2.96 5 mm package information figure 46. wlcsp49 - 0.4 mm pitch wafer level chip scale package outline 1. drawing is not to scale. ! o r i e n t a t i o n r e f e r e n c e 7 a f e r b a c k s i d e % $ $ e t a i l ! r o t a t e d ? 3 e a t i n g p l a n e . o t e ! " u m p b 3 i d e v i e w ! ! $ e t a i l ! e & ' e e ! b a l l l o c a t i o n e % ! " u m p s i d e e e e : . o t e & r o n t v i e w ! 6 ! ? - % ? 6 ' ! package information stm32f401xb stm32f401xc 115/135 docid024738 rev 6 figure 47. wlcsp49 0.4 mm pitch wafer level chip scale recommended footprint table 79. wlcsp49 - 49-ball, 2.965 x 2.965 mm, 0.4 mm pitch wafer level chip scale package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 0.525 0.555 0.585 0.0207 0.0219 0.0230 a1 - 0.175 - - 0.0069 - a2 - 0.380 - - 0.0150 - a3 (2) 2. back side coating. - 0.025 - - 0.0010 - b (3) 3. dimension is measured at the maximum bum p diameter parallel to primary datum z. 0.220 0.250 0.280 0. 0087 0.0098 0.0110 d 2.930 2.965 3.000 0. 1154 0.1167 0.1181 e 2.930 2.965 3.000 0. 1154 0.1167 0.1181 e - 0.400 - - 0.0157 - e1 - 2.400 - - 0.0945 - e2 - 2.400 - - 0.0945 - f - 0.2825 - - 0.0111 - g - 0.2825 - - 0.0111 - aaa - 0.100 - - 0.0039 - bbb - 0.100 - - 0.0039 - ccc - 0.100 - - 0.0039 - ddd - 0.050 - - 0.0020 - eee - 0.050 - - 0.0020 - 0 6 9 ' v p ' s d g docid024738 rev 6 116/135 stm32f401xb stm32f401xc package information 130 wlcsp49 device marking the following figure gives an example of topside marking orientation versus ball a1 identifier location. other optional marking or inse t/upset marks, which depend on supply chain operations, are not indicated below. figure 48. wlcsp49 marking example (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. table 80. wlcsp49 recommended pcb design rules (0.4 mm pitch) dimension recommended values pitch 0.4 mm dpad 260 m max. (circular) 220 m recommended dsm 300 m min. (for 260 m diameter pad) pcb pad design non-solder mask defined via underbump allowed 0 6 y 9 ) % < < : : 3 u r g x f w l g h q w l i l f d w l r q % d o o $ l q g h q w l i l h u ' d w h f r g h 5 h y l v l r q f r g h 5 package information stm32f401xb stm32f401xc 117/135 docid024738 rev 6 7.2 ufqfpn48 package information figure 49. ufqfpn48 - 48-l ead, 7 x 7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package outline 1. drawing is not to scale. 2. all leads/pads should also be soldered to the pcb to improve the lead/pad solder joint life. 3. there is an exposed die pad on the underside of t he ufqfpn package. it is recommended to connect and solder this back-side pad to pcb ground. $ % b 0 ( b 9 ' 3 l q l g h q w l i l h u o d v h u p d u n l q j d u h d ( ( ' < ' ( ( [ s r v h g s d g d u h d = ' h w d l o = 5 w \ s / & [ ? s l q f r u q h u $ 6 h d w l q j s o d q h $ e h g g g ' h w d l o < 7 table 81. ufqfpn48 - 48-lead, 7 x 7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package mechanical data symbol millimeters inches (1) min. typ. max. min. typ. max. a 0.500 0.550 0.600 0.0197 0.0217 0.0236 a1 0.000 0.020 0.050 0.0000 0.0008 0.0020 d 6.900 7.000 7.100 0.2717 0.2756 0.2795 e 6.900 7.000 7.100 0.2717 0.2756 0.2795 d2 5.500 5.600 5.700 0.2165 0.2205 0.2244 docid024738 rev 6 118/135 stm32f401xb stm32f401xc package information 130 figure 50. ufqfpn48 - 48-lead, 7 x 7 mm , 0.5 mm pitch, ultra thin fine pitch quad flat recommended footprint 1. dimensions are in millimeters. e2 5.500 5.600 5.700 0.2165 0.2205 0.2244 l 0.300 0.400 0.500 0.0118 0.0157 0.0197 t - 0.152 - - 0.0060 - b 0.200 0.250 0.300 0.0079 0.0098 0.0118 e - 0.500 - - 0.0197 - ddd - - 0.080 - - 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. table 81. ufqfpn48 - 48-lead, 7 x 7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package mechanical data (continued) symbol millimeters inches (1) min. typ. max. min. typ. max. ! " ? & 0 ? 6 package information stm32f401xb stm32f401xc 119/135 docid024738 rev 6 ufqfpn48 device marking the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. other optional marking or inse t/upset marks, which depend on supply chain operations, are not indicated below. figure 51. ufqfpn48 marking example (top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 0 v y 9 6 7 0 ) & % 8 < : : 5 3 l q l g h q w l i l h u 3 u r g x f w l g h q w l i l f d w l r q ' d w h f r g h 5 h y l v l r q f r g h docid024738 rev 6 120/135 stm32f401xb stm32f401xc package information 130 7.3 lqfp64 package information figure 52. lqfp64 - 64-pin, 10 x 10 mm, 64-pi n low-profile quad flat package outline 1. drawing is not to scale. : b 0 ( b 9 $ $ $ 6 ( $ 7 , 1 * 3 / $ 1 ( f f f & e & f $ / / . , ' ( 1 7 , ) , & $ 7 , 2 1 3 , 1 ' ' ' h ( ( ( * $ 8 * ( 3 / $ 1 ( p p package information stm32f401xb stm32f401xc 121/135 docid024738 rev 6 figure 53. lqfp64 recommended footprint 1. dimensions are in millimeters. table 82. lqfp64 - 64-pin, 10 x 10 mm, 64-pin low-profile quad flat package mechanical data symbol millimeters inches (1) min. typ. max. min. typ. max. a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d - 12.000 - - 0.4724 - d1 - 10.000 - - 0.3937 - e - 12.000 - - 0.4724 - e1 - 10.000 - - 0.3937 - e3 - 7.5000 - - 0.2953 - e - 0.500 - - 0.0197 - k 03.57 03.57 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1. values in inches are converted fr om mm and rounded to 4 decimal digits. a i c docid024738 rev 6 122/135 stm32f401xb stm32f401xc package information 130 lqfp64 device marking the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. other optional marking or inse t/upset marks, which depend on supply chain operations, are not indicated below. figure 54. lqfp64 marking example (top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 0 6 y 9 5 h y l v l r q f r g h 6 7 0 ) 5 % 7 3 u r g x f w l g h q w l i l f d w l r q ' d w h f r g h < : : 3 l q l q g h q w l i l h u 5 package information stm32f401xb stm32f401xc 123/135 docid024738 rev 6 7.4 lqfp100 package information figure 55. lqfp100 - 100-pin, 14 x 14 mm, 100-pin low-profile quad flat package outline 1. drawing is not to scale. e ) $ % . 4 ) & ) # ! 4 ) / . 0 ) . ' ! 5 ' % 0 , ! . % m m 3 % ! 4 ) . ' 0 , ! . % $ $ $ % % % + c c c # # , ? - % ? 6 ! ! ! , , c b ! docid024738 rev 6 124/135 stm32f401xb stm32f401xc package information 130 figure 56. lqfp100 recommended footprint 1. dimensions are in millimeters. table 83. lqpf100- 100-pin, 14 x 14 mm, 100-pin low-profile quad flat package mechanical data symbol millimeters inches (1) min. typ. max. min. typ. max. a - - 1.60 - - 0.063 a1 0.050 - 0.150 0.002 - 0.0059 a2 1.350 1.40 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d 15.800 16.000 16.200 0.622 0.6299 0.6378 d1 13.800 14.000 14.200 0.5433 0.5512 0.5591 d3 - 12.000 - - 0.4724 - e 15.800 16.000 16.200 0.622 0.6299 0.6378 e1 13.800 14.000 14.200 0.5433 0.5512 0.5591 e3 - 12.000 - - 0.4724 - e - 0.500 - - 0.0197 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - k 0.0 3.5 7.0 0.0 3.5 7.0 ccc 0.080 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. a i c package information stm32f401xb stm32f401xc 125/135 docid024738 rev 6 lqfp100 device marking the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. other optional marking or inse t/upset marks, which depend on supply chain operations, are not indicated below. figure 57. lqpf100 marking example (top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 0 6 y 9 ( 6 ) 9 % 7 5 5 h y l v l r q f r g h 3 u r g x f w l g h q w l i l f d w l r q ' d w h f r g h 3 l q l q g h q w l i l h u < : : docid024738 rev 6 126/135 stm32f401xb stm32f401xc package information 130 7.5 ufbga100 package information figure 58. ufbga100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package outline 1. drawing is not to scale. table 84. ufbga100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data symbol millimeters inches (1) min. typ. max. min. typ. max. a 0.460 0.530 0.600 0.0181 0.0209 0.0236 a1 0.050 0.080 0.110 0.0020 0.0031 0.0043 a2 0.400 0.450 0.500 0.0157 0.0177 0.0197 a3 - 0.130 - - 0.0051 - a4 0.270 0.320 0.37 0 0.0106 0.0126 0.0146 b 0.240 0.290 0.340 0.0094 0.0114 0.0134 d 6.950 7.000 7.050 0.2736 0.2756 0.2776 d1 5.450 5.500 5.55 0 0.2146 0.2165 0.2185 e 6.950 7.000 7.050 0.2736 0.2756 0.2776 e1 5.450 5.500 5.55 0 0.2146 0.2165 0.2185 e - 0.500 - - 0.0197 - f 0.700 0.750 0.800 0 .0276 0.0295 0.0315 $ & b 0 ( b 9 6 h d w l q j s o d q h $ h ) ) ' 0 ? e e d o o v $ ( 7 2 3 9 , ( : % 2 7 7 2 0 9 , ( : $ e d o o l g h q w l i l h u h $ $ < ; = g g g = ' ( h h h = < ; i i i ? ? 0 0 = $ $ $ e d o o l q g h [ d u h d package information stm32f401xb stm32f401xc 127/135 docid024738 rev 6 figure 59. ufbga100 - 100-ball, 7 x 7 mm, 0. 50 mm pitch, ultra fine pitch ball grid array package recommended footprint ddd - - 0.100 - - 0.0039 eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. values in inches are converted from mm and rounded to 4 decimal digits. table 85. ufbga100 recommended pcb design rules (0.5 mm pitch bga) dimension recommended values pitch 0.5 dpad 0.280 mm dsm 0.370 mm typ. (depends on the soldermask reg- istration tolerance) stencil opening 0.280 mm stencil thickness between 0.100 mm and 0.125 mm table 84. ufbga100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data (continued) symbol millimeters inches (1) min. typ. max. min. typ. max. $ & b ) 3 b 9 ' s d g ' v p docid024738 rev 6 128/135 stm32f401xb stm32f401xc package information 130 ufbga100 device marking the following figure gives an example of topside marking orientation versus ball a1 identifier location. other optional marking or inse t/upset marks, which depend on supply chain operations, are not indicated below. figure 60. ufbga100 marking example (top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 0 6 y 9 6 7 0 ) 9 % + < : : 3 u r g x f w l g h q w l i l f d w l r q 5 h y l v l r q f r g h 5 ' d w h f r g h % d o o l q g h q w l i l h u package information stm32f401xb stm32f401xc 129/135 docid024738 rev 6 7.6 thermal characteristics the maximum chip junction temperature (t j max) must never exceed the values given in table 14: general operating conditions on page 59 . the maximum chip-junction temperature, t j max., in degrees cels ius, may be calculated using the following equation: t j max = t a max + (pd max x ja ) where: ? t a max is the maximum ambient temperature in c, ? ja is the package junction-to-ambient thermal resistance, in c/w, ? pd max is the sum of p int max and p i/o max (pd max = p int max + p i/o max), ? p int max is the product of i dd and v dd , expressed in watts. th is is the maximum chip internal power. p i/o max represents the maximum power dissipation on output pins where: p i/o max = (v ol i ol ) + ((v dd ? v oh ) i oh ), taking into account the actual v ol / i ol and v oh / i oh of the i/os at low and high level in the application. 7.6.1 reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). available from www.jedec.org. table 86. package thermal characteristics symbol parameter value unit ja thermal resistance junction-ambient ufqfpn48 32 c/w thermal resistance junction-ambient wlcsp49 52 thermal resistance junction-ambient lqfp64 50 thermal resistance junction-ambient lqfp100 42 thermal resistance junction-ambient ufbga100 56 docid024738 rev 6 130/135 stm32f401xb stm32f401xc part numbering 130 8 part numbering table 87. ordering information scheme example: stm32 f 401 c c t 6 xxx device family stm32 = arm-based 32-bit microcontroller product type f = general-purpose device subfamily 401: 401 family pin count c = 48/49 pins r = 64 pins v = 100 pins flash memory size b = 128 kbytes of flash memory c = 256 kbytes of flash memory package h = ufbga t = lqfp u = ufqfpn y = wlcsp temperature range 6 = industrial temperature range, ?40 to 85 c 7 = industrial temperature range, ?40 to 105 c packing tr = tape and reel tt = tape and reel for wlcsp as per pcn9547 (1) 1. to get this document, please contact your nearest st sales office. no character = tray or tube revision history stm32f401xb stm32f401xc 131/135 docid024738 rev 6 9 revision history table 88. document revision history date revision changes 23-jul-2013 1 initial release. 06-sep-2013 2 updated product status to production data added i2c 1 mbit/s in features updated figure 1: compatible board design for lqfp100 package added notes and revised the main function after reset columnn table 8: stm32f401xb/stm32f401xc pin definitions . replaced ?i2s2_ckin? signal name with ?i2s_ckin? and added eventout alternat e function in table 8: stm32f401xb/stm32f401xc pin definitions and table 9: alternate function mapping updated section 3.28: analog-to-digital converter (adc) updated the reference of v esd(cdm) in table 51: esd absolute maximum ratings updated section 3.20: inter-integrated circuit interface (i2c) , including table 5: comparison of i2c analog and digital filters removed first sentence (?unless otherwise specified...?) in i2c interface characteristics changed the order of the tables in section 6.3.6: supply current characteristics modified the ?sda and scl rise time ? fast mode i2c minimum value in table 59: i 2 c characteristics updated figure 33: i 2 c bus ac waveforms and measurement circuit and table 60: scl frequency (f pclk1 = 42 mhz, v dd = v dd_i2c = 3.3 v) replaced ?marking of engineering samples? sections with ?marking of samples? sections, and added ufbga100 device marking section for package ufgba100 in section 7: package information 08-nov-2013 3 updated ufbga100 in table 86: package thermal characteristics . changed wlcsp49 package measurements to 3 x 3 mm in section 7.1 . docid024738 rev 6 132/135 stm32f401xb stm32f401xc revision history 134 16-may-2014 4 change v dd /v dda minimum value to 1.7 v. changed number of exti lines in section 3.10: external interrupt/event controller (exti) . updated figure 18: power supply scheme . updated table 11: voltage characteristics , table 12: current characteristics and table 14: general operating conditions . added note 4. in table 26: typical and maximum current consumption in sleep mode . updated typical values at t a = 25 c in table 27: typical and maximum current consumptions in stop mode - v dd =1.8 v . updated sdio current consumption in table 33: peripheral current consumption . updated table 54: i/o static characteristics , table 56: i/o ac characteristics and added figure 30: ft i/o input characteristics . updated table 55: output voltage characteristics . updated table 53: i/o current injection susceptibility and table 57: nrst pin characteristics . updated table 61: spi dynamic characteristics . updated package dimensions in section 7.1 title. added note below engineering sample marking schematics. updated ufbga100 thermal resistance in table 86: package thermal characteristics . table 88. document revision history (continued) date revision changes revision history stm32f401xb stm32f401xc 133/135 docid024738 rev 6 06-aug-2015 5 changed current consumption to 128 a/mhz on cover page. updated table 3: regulator on/off and internal power supply supervisor availability for ufqfpn48. updated figure 10: stm32f401xb/stm32f401xc wlcsp49 pinout to show top view instead of bump view. renamed vcap1/2 in to vcap_1/_2 in figure 10: stm32f401xb/stm32f401xc wlcsp49 pinout , figure 11: stm32f401xb/stm32f401xc ufqfpn48 pinout , figure 13: stm32f401xb/stm32f401xc lqfp100 pinout and figure 14: stm32f401xb/stm32f401xc ufbga100 pinout . in whole section 6: electrical characteristics , modified notes related to characteristics guaranteed by design and by tests during characterization. updated pls[2:0]=101 (falling edge) in table 19: embedded reset and power control block characteristics . updated table 39: hsi oscillator characteristics . updated v hys in table 56: i/o ac characteristics . added t sp in table 59: i 2 c characteristics . removed note 1 in table 67: adc accuracy at f adc = 18 mhz , table 68: adc accuracy at f adc = 30 mhz and table 69: adc accuracy at f adc = 36 mhz . added wlcsp49 figure 47: wlcsp49 0.4 mm pitch wafer level chip scale recommended footprint and table 80: wlcsp49 recommended pcb design rules (0.4 mm pitch) . added section : wlcsp49 device marking . updated section : ufqfpn48 device marking . updated table 82: lqfp64 - 64-pin, 10 x 10 mm, 64-pin low-profile quad flat package mechanical data and section : lqfp64 device marking . updated section : lqfp64 device marking and section : lqfp100 device marking updated table 84: ufbga100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data , figure 59: ufbga100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package recommended footprint . added ta ble 85 : ufbga100 recommended pcb design rules (0.5 mm pitch bga) . updated section : ufbga100 device marking . added temperature range 7 in table 87: ordering information scheme . table 88. document revision history (continued) date revision changes docid024738 rev 6 134/135 stm32f401xb stm32f401xc revision history 134 07-sep-2016 6 features : added dynamic efficiency, otp memory and ecopack ? 2 compliance, updated clock/reset and supply management features. updated signal corresponding to pin 21 in figure 13: stm32f401xb/stm32f401xc lqfp100 pinout . updated pb11 alternate functions in table 8: stm32f401xb/stm32f401xc pin definitions and table 9: alternate function mapping . added reference to v ref- for |v ssx ? v ss | in table 11: voltage characteristics . updated figure 26: acc hsi versus temperature . updated v il minimum value and note related to v ih minimum value in table 54: i/o static characteristics . added note related to external capacitor below figure 32: recommended nrst pin protection . updated t h(nss) in figure 34: spi timing diagram - slave mode and cpha = 0 and figure 35: spi timing diagram - slave mode and cpha = 1 (1) . added v ref- in table 66: adc characteristics . section 7: package information : ? added note related to optional marking and inset/upset marks in all package marking sections. ? updated b dimension in table 84: ufbga100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data . added new tt packing in section 8: part numbering . table 88. document revision history (continued) date revision changes stm32f401xb stm32f401xc 135/135 docid024738 rev 6 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 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